Mohamad Jahanbani

US Patent:

7214590, May 8, 2007

Filed:

Apr 5, 2005

Appl. No.:

11/098874

Inventors:

Sangwoo Lim - Austin TX, US
Paul A. Grudowski - Austin TX, US
Mohamad M. Jahanbani - Austin TX, US
Hsing H. Tseng - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438287, 438585, 438591

Abstract:

A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.

US Patent:

7491622, Feb 17, 2009

Filed:

Apr 24, 2006

Appl. No.:

11/409790

Inventors:

Michael D. Turner - San Antonio TX, US
Mohamad M. Jahanbani - Austin TX, US
Toni D. Van Gompel - Austin TX, US
Mark D. Hall - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/76
H01L 23/58

US Classification:

438438, 257647

Abstract:

A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.

US Patent:

7670895, Mar 2, 2010

Filed:

Apr 24, 2006

Appl. No.:

11/409633

Inventors:

Toni D. Van Gompel - Austin TX, US
Peter J. Beckage - Austin TX, US
Mohamad M. Jahanbani - Austin TX, US
Michael D. Turner - San Antonio TX, US

Assignee:

Freescale Semiconductor, Inc - Austin TX

International Classification:

H01L 21/8238

US Classification:

438221, 438425, 438437, 257E21549

Abstract:

A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

US Patent:

20050130359, Jun 16, 2005

Filed:

Dec 16, 2003

Appl. No.:

10/737115

Inventors:

Toni Van Gompel - Austin TX, US
Mark Hall - Austin TX, US
Mohamad Jahanbani - Austin TX, US
Michael Turner - San Antonio TX, US

International Classification:

H01L021/336
H01L021/8234

US Classification:

438197000

Abstract:

A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.

US Patent:

20060115949, Jun 1, 2006

Filed:

Dec 1, 2004

Appl. No.:

11/000717

Inventors:

Da Zhang - Austin TX, US
Mohamad Jahanbani - Austin TX, US
Ross Noble - Austin TX, US

International Classification:

H01L 21/336
H01L 21/44

US Classification:

438300000, 438301000, 438607000

Abstract:

A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NHOH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially to fill the source/drain recesses and thereby create source/drain structures. Exposed dielectric on the substrate upper surface may be removed using an HF dip prior to forming the source/drain recesses. Preferably, the NHOH solution has an NHOH concentration of less than approximately 0.5% and is maintained a temperature in the range of approximately 20 to 35 C. The silicon-bearing epitaxial compound may be silicon germanium for PMOS transistor or silicon carbide for NMOS transistors. A silicon dry etch process may be performed prior to the NHOH wet etch to remove a surface portion of the source/drain regions.

US Patent:

20060234467, Oct 19, 2006

Filed:

Apr 15, 2005

Appl. No.:

11/106822

Inventors:

Toni Van Gompel - Austin TX, US
Glenn Abeln - Austin TX, US
Peter Beckage - Austin TX, US
Kyle Gilliland - Pflugerville TX, US
Mohamad Jahanbani - Austin TX, US
James Burnett - Austin TX, US

International Classification:

H01L 21/76

US Classification:

438424000, 438425000

Abstract:

Divots () may particularly be a problem for isolation trenches () that are shallow. These divots () may have a negative impact on the performance of the integrated circuit (). Densification heating may be used to reduce the size and/or depth of these divots () during manufacturing. For example, densification heating may be done at a temperature of at least 1100 degrees Celsius for at least 10 minutes after filling the isolation trenches () with dielectric material (). This densification heating may improve the variation in threshold voltages of transistors (e.g. ) on an integrated circuit (), particularly SOI (silicon on insulator) devices. SRAM cells () in particular may benefit from this densification heating.

US Patent:

20070295357, Dec 27, 2007

Filed:

Jun 27, 2006

Appl. No.:

11/426755

Inventors:

Michael Lovejoy - Austin TX, US
Ross Noble - Austin TX, US
Mohamad Jahanbani - Austin TX, US

International Classification:

C23G 1/00
H01L 21/306

US Classification:

134002000, 156345110

Abstract:

A method of removing a metal includes exposing at least a portion of a metal-to-metal removal chemistry, wherein the metal removal chemistry comprises a chlorine-rich superoxidizer. In one embodiment, the metal being removed is a metal, such as a noble metal, that did not react with the semiconductor device during a salicidation process. In one embodiment, the chlorine-rich superoxidizer is formed by mixing hydrochloric acid in gas form with hydrogen peroxide and sulfuric acid. The metal can be exposed to the chlorine-rich superoxidizer in various ways, such as through an immersion or spray process.