Mohammad Ahdel Abdallah

US Patent:

6377970, Apr 23, 2002

Filed:

Mar 31, 1998

Appl. No.:

09/052904

Inventors:

Mohammad A. Abdallah - Folsom CA
Vladimir Pentkovski - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 752

US Classification:

708603, 712 22

Abstract:

A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

US Patent:

6426746, Jul 30, 2002

Filed:

Mar 31, 1998

Appl. No.:

09/053390

Inventors:

Hsien-Cheng E. Hsieh - Gold River CA
Mohammad Abdallah - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1500

US Classification:

345419

Abstract:

The present invention discloses a method and apparatus for optimizing three-dimensional (3-D) transformation on N vertices of a data object based on a transformation matrix of size KÃK. The method comprises: storing coordinates of the N vertices in K data items, each of the K data items having N elements; and scheduling a sequence of M operations with a set of P storage elements, the sequence of M operations performing a matrix multiplication of the transformation matrix with the K data items to produce transformed K data items, the set of P storage elements storing a plurality of intermediate results produced by the sequence of M operations.

US Patent:

6498605, Dec 24, 2002

Filed:

Nov 18, 1999

Appl. No.:

09/442663

Inventors:

Mohammad A. Abdallah - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1540

US Classification:

345422

Abstract:

An efficient way to determine which objects in a 3D image are to be displayed and which are not because they are obscured by other displayed objects. Displayable elements are assigned depth values defining their relative perceived nearness to the viewer of the image. A comparison of depth values determines which elements are to be displayed and which are not to be displayed because they are obscured by displayed elements. Rather than comparing the depth value of every pixel in a displayable object to determine whether it is to be displayed, the invention compares groups of pixels defined by spans. Minimum and maximum depth values are determined for each span so that depth variations within a span can be accommodated. Masks are used when only partial spans are to be considered because some pixels in a span are outside the pixel boundaries being considered in a particular comparison.

US Patent:

6584549, Jun 24, 2003

Filed:

Dec 29, 2000

Appl. No.:

09/749936

Inventors:

Mohammad A. Abdallah - Folsom CA
Khalid Al-Dajani - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711137

Abstract:

A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

US Patent:

6701414, Mar 2, 2004

Filed:

May 2, 2003

Appl. No.:

10/427908

Inventors:

Mohammad A. Abdallah - Folsom CA
Khalid Al-Dajani - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711137

Abstract:

A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

US Patent:

6718440, Apr 6, 2004

Filed:

Sep 28, 2001

Appl. No.:

09/966587

Inventors:

Subramaniam Maiyuran - Gold River CA
Vivek Garg - Folsom CA
Mohammad A. Abdallah - Folsom CA
Jagannath Keshava - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711137, 711117, 711122, 711154

Abstract:

A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.

US Patent:

6754812, Jun 22, 2004

Filed:

Jul 6, 2000

Appl. No.:

09/610895

Inventors:

Mohammad A. Abdallah - Folsom CA
Khalid D. Al-Dajani - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 938

US Classification:

712234

Abstract:

An instruction associated with a condition is executed when the condition is resolved. In executing the instruction, a first operation designated by the instruction is performed to produce a first result, and a second operation is performed to produce a second result. The first result or the second result is output based on how the condition is resolved.

US Patent:

6918032, Jul 12, 2005

Filed:

Jul 6, 2000

Appl. No.:

09/611282

Inventors:

Mohammad A. Abdallah - Folsom CA, US
Khalid D. Al-Dajani - Orangevale CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F009/38

US Classification:

712234, 712216

Abstract:

An instruction associated with a condition is executed. In executing the instruction, a first operation designated by the instruction is performed to produce a first result, and a second operation is performed to produce a second result. Both the first result and the second result are associated with the condition.