Mohammad K Abdallah

US Patent:

20080077772, Mar 27, 2008

Filed:

Sep 22, 2006

Appl. No.:

11/526065

Inventors:

Ronen Zohar - Sunnyvale CA, US
Mohammad Abdallah - Folsom CA, US
Boris Sabanin - N. Novgorod Region, RU
Mark Seconi - Beaverton OR, US

International Classification:

G06F 9/30

US Classification:

712208, 712220

Abstract:

A method and apparatus for including in a processor instructions for performing select operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein first packed data in a source operand and a second packed data in a destination operand. The processor selects the first packed data if the control bit for the source operand is set to “1” and stores the data into the destination operand. Otherwise, the processor keeps the data in the destination operand. The final value of the destination operand is stored in memory.

US Patent:

20120198122, Aug 2, 2012

Filed:

Jan 27, 2012

Appl. No.:

13/359832

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Clara CA

International Classification:

G06F 12/08
G06F 12/10

US Classification:

711 3, 711E12061, 711E12017, 711E12018, 711E12024

Abstract:

A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

US Patent:

20120198157, Aug 2, 2012

Filed:

Jan 27, 2012

Appl. No.:

13/359767

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711118, 711E12017

Abstract:

A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

US Patent:

20120198168, Aug 2, 2012

Filed:

Jan 27, 2012

Appl. No.:

13/359939

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Cruz CA

International Classification:

G06F 12/08

US Classification:

711125, 711E1202

Abstract:

A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of a storage stack, wherein the pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack, and allocating a group of storage blocks of the storage stack, wherein the size of the allocation is in accordance with a corresponding size of one of the plurality of different size groups. Upon a hit on the tag, a corresponding entry is accessed to retrieve a pointer that indicates where in the storage stack a corresponding group of storage blocks of converted native instructions reside. The converted native instructions are then fetched from the storage stack for execution.

US Patent:

20120198209, Aug 2, 2012

Filed:

Jan 27, 2012

Appl. No.:

13/359817

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Clara CA

International Classification:

G06F 9/30
G06F 9/38

US Classification:

712206, 712226, 712E09016, 712E0906, 712E09021, 712E09075, 712E09055

Abstract:

A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch. The method further includes assembling a guest instruction block from the instruction sequence. The guest instruction block is translated to a corresponding native conversion block, wherein an at least one native far branch that corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch. Upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.

US Patent:

20120246448, Sep 27, 2012

Filed:

Mar 23, 2012

Appl. No.:

13/428452

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Clara CA

International Classification:

G06F 9/312

US Classification:

712214, 712E09033

Abstract:

A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

US Patent:

20120246450, Sep 27, 2012

Filed:

Mar 23, 2012

Appl. No.:

13/428438

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712216, 712E09016, 712E09028

Abstract:

A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

US Patent:

20120246657, Sep 27, 2012

Filed:

Mar 23, 2012

Appl. No.:

13/428440

Inventors:

Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC. - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.