Mohammad Y Maniar

age ~76

from Saratoga, CA

Also known as:
  • Mohammad T Maniar
  • Yasmin B Maniar
  • Yasmin M Maniar
Phone and address:
21200 Canyon View Dr, Saratoga, CA 95070
4087415130

Mohammad Maniar Phones & Addresses

  • 21200 Canyon View Dr, Saratoga, CA 95070 • 4087415130
  • Fresno, CA
  • San Jose, CA
  • Bronx, NY
  • Trinidad, CA

Work

  • Position:
    Professional/Technical

Education

  • Degree:
    Graduate or professional degree

Emails

Us Patents

  • Network Interface With Security Association Data Prefetch For High Speed Offloaded Security Processing

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  • US Patent:
    7502474, Mar 10, 2009
  • Filed:
    May 6, 2004
  • Appl. No.:
    10/839872
  • Inventors:
    Marufa Kaniz - Santa Clara CA, US
    Jeffrey Dwork - San Jose CA, US
    Robert Alan Williams - Cupertino CA, US
    Mohammad Maniar - Saratoga CA, US
    Somnath Viswanath - Bangalore, IN
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H04K 1/00
  • US Classification:
    380255, 713189, 713192
  • Abstract:
    One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system selectively perform security processing on data incoming from the network based on security associations stored in a memory external to the network interface system, typically a host system memory. The security association for any given frame, when available, is fetched from the external memory after the frame begins to arrive in the network interface system based in part on information contained in the frame. Preferably, the fetch begins before the frame is fully received and the security association is queued whereby security processing can begin without having to wait for the security association to be fetched.
  • Receive Ipsec In-Line Processing Of Mutable Fields For Ah Algorithm

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  • US Patent:
    7512787, Mar 31, 2009
  • Filed:
    Feb 3, 2004
  • Appl. No.:
    10/771019
  • Inventors:
    Somnath Viswanath - San Jose CA, US
    Mohammad Maniar - Saratoga CA, US
    Jeffrey Dwork - San Jose CA, US
    Robert Alan Williams - Cupertino CA, US
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H04L 9/00
  • US Classification:
    713160
  • Abstract:
    The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system is operative to selectively authenticate incoming and outgoing data. The security system includes a pipeline that masks mutable fields from incoming data prior to authentication.
  • Security Association Table Lookup Architecture And Method Of Operation

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  • US Patent:
    7624263, Nov 24, 2009
  • Filed:
    Sep 21, 2004
  • Appl. No.:
    10/945802
  • Inventors:
    Somnath Viswanath - Bangalore, IN
    Jeffrey Dwork - San Jose CA, US
    Robert Alan Williams - Cupertino CA, US
    Marufa Kaniz - Santa Clara CA, US
    Mohammad Y. Maniar - Saratoga CA, US
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H04L 29/06
  • US Classification:
    713151, 713153, 713160, 726 13, 726 14
  • Abstract:
    A security association architecture system of the present invention facilitates network data transfer by providing an internal portion of a security association database that can be quickly accessed to obtain security associations as well as an external component that stores the complete security association database. As a result, at least some security associations for incoming received frames and outgoing transmitted frames can be obtained from the internal portion located on a network interface device without accessing system memory, a host computer, and the like in order to obtain the security associations to perform security processing.
  • Two Parallel Engines For High Speed Transmit Ipsec Processing

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  • US Patent:
    7685434, Mar 23, 2010
  • Filed:
    Mar 2, 2004
  • Appl. No.:
    10/791557
  • Inventors:
    Marufa Kaniz - Santa Clara CA, US
    Jeffrey Dwork - San Jose CA, US
    Robert Alan Williams - Cupertino CA, US
    Mohammad Y. Maniar - Saratoga CA, US
    Somnath Viswanath - San Jose CA, US
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G06F 21/00
    G06F 11/30
  • US Classification:
    713189
  • Abstract:
    The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.
  • Circuit For Controlling External Bipolar Buffers From An Mos Peripheral Device

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  • US Patent:
    45946540, Jun 10, 1986
  • Filed:
    Nov 4, 1983
  • Appl. No.:
    6/549521
  • Inventors:
    Mohammad Y. Maniar - San Jose CA
    Steven Dines - San Jose CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G06F 300
    G06F 922
    G06F 1342
  • US Classification:
    364200
  • Abstract:
    A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode logic block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer to transmit data signals from the peripheral device to a system bus. The circuit also provides for a second slave mode logic block and a master mode logic block for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer to transmit data signals from the system bus to the peripheral device. Each slave mode logic block is responsive to condiion signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the periphel device so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.

Youtube

princess yamna amin deemak (chera-e-zan)

MY TELEFILM DIRECTOR : NAIN MANIAR PRODUCER : AKHTAR HUSNAIN CAST : PR...

  • Category:
    Entertainment
  • Uploaded:
    25 Dec, 2010
  • Duration:
    1m 24s

Harsukh Maniar

Songs of Md rafi

  • Category:
    Music
  • Uploaded:
    06 Nov, 2010
  • Duration:
    1m 11s

Mylife

Mohammad Maniar Photo 1

Milap Maniar El Paso TX

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Mita Maniar Mitul Maniar Mohammad Maniar Mohammed Maniar Mohammed Maniar

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