Mohammed F Hasan

US Patent:

20220416044, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/359440

Inventors:

- Santa Clara CA, US
Mohammed HASAN - Aloha OR, US
Vivek THIRTHA - Portland OR, US
Nikhil MEHTA - Portland OR, US
Tahir GHANI - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/786
H01L 29/08
H01L 27/092

Abstract:

Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires. The epitaxial growth occurs inside a mold confinement, and due the mold, the lateral wingspan of the wingspan of the epitaxial growth is limited. Also the mold causes the epitaxial source or drain structures to exhibit substantially vertical opposing sidewalls and a top surface having a generally mushroom shape over a top of a dielectric layer.