Moinuddin K Qureshi

US Patent:

8004884, Aug 23, 2011

Filed:

Jul 31, 2009

Appl. No.:

12/533548

Inventors:

Michele M. Franceschini - Yorktown Heights NY, US
Moinuddin K. Qureshi - Yorktown Heights NY, US
Vijayalakshmi Srinivasan - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00

US Classification:

365163, 36518916

Abstract:

Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.

US Patent:

8161242, Apr 17, 2012

Filed:

Aug 1, 2008

Appl. No.:

12/184737

Inventors:

Moinuddin K. Qureshi - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02

US Classification:

711122, 711118, 711119, 711120, 711133, 711134, 711135, 711170

Abstract:

Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates that a plurality of non-dedicated cache sets within the cache should operate as spill cache sets or receive cache sets. The cache controller sets the plurality of non-dedicated cache sets to spill an evicted cache line to an associated cache set in another cache in the event of a cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the spill cache sets. The cache controller sets the plurality of non-dedicated cache sets to receive an evicted cache line from another cache set in the event of the cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the receive cache sets.

US Patent:

8250303, Aug 21, 2012

Filed:

Sep 30, 2009

Appl. No.:

12/570440

Inventors:

Kerry Bernstein - Underhill VT, US
Moinuddin K. Qureshi - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 12/00

US Classification:

711118, 711170, 711E12041

Abstract:

A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.

US Patent:

8356153, Jan 15, 2013

Filed:

Nov 19, 2010

Appl. No.:

12/950522

Inventors:

Michele M. Franceschini - White Plains NY, US
John P. Karidis - Ossining NY, US
Moinuddin K. Qureshi - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

711165, 711103, 711154, 711156

Abstract:

Adaptive write leveling in a memory system that includes a memory that has one or more limited lifetime memory devices and an adaptive write leveling module connected to the memory. The adaptive write leveling module is operative for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.

US Patent:

8417917, Apr 9, 2013

Filed:

Sep 30, 2009

Appl. No.:

12/570351

Inventors:

Philip G. Emma - Danbury CT, US
Eren Kursun - Ossining NY, US
Moinuddin K. Qureshi - White Plains NY, US
Vijayalakshmi Srinivasan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/00

US Classification:

712 10, 712 11, 712 13, 712 15

Abstract:

A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores.

US Patent:

8458501, Jun 4, 2013

Filed:

Jul 27, 2010

Appl. No.:

12/844372

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Christopher J. Gonzalez - Shelburne VT, US
Moinuddin K. Qureshi - White Plains NY, US
Victor Zyuban - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32
G06F 3/00

US Classification:

713320, 710 18

Abstract:

A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.

US Patent:

20040230780, Nov 18, 2004

Filed:

May 12, 2003

Appl. No.:

10/436397

Inventors:

Brian Prasky - Wappingers Falls NY, US
Moinuddin Qureshi - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/44

US Classification:

712/238000

Abstract:

Disclosed is a method and apparatus providing the capability to create a dynamic associative branch target buffer (BTB). A dynamically based associative BTB allows for either an increase number of entries and/or a reduction in area over current based static based BTBs while up to retaining the same confidence level of prediction accuracy.

US Patent:

20050120193, Jun 2, 2005

Filed:

Dec 1, 2003

Appl. No.:

10/724815

Inventors:

Philip Emma - Danbury CT, US
Allan Hartstein - Chappaqua NY, US
Brian Prasky - Wappingers Falls NY, US
Thomas Puzak - Ridgefield CT, US
Moinuddin Ahmed Qureshi - Austin TX, US
Vijayalakshmi Srinivasan - New York NY, US

International Classification:

G06F009/00

US Classification:

712240000

Abstract:

A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.