Monica Gu Gupta

US Patent:

20200272513, Aug 27, 2020

Filed:

Jan 13, 2020

Appl. No.:

16/740794

Inventors:

- Santa Clara CA, US
Vijay Dhanraj - Beaverton OR, US
Russell J. Fenger - Beaverton OR, US
Vivek Garg - Folsom CA, US
Eugene Gorbatov - Hillsboro OR, US
Stephen H. Gunther - Beaverton OR, US
Monica Gupta - Hillsboro OR, US
Efraim Rotem - Haifa, IL
Krishnakanth V. Sistla - Beaverton OR, US
Guy M. Therien - Beaverton OR, US
Ankush Varma - Hillsboro OR, US
Eliezer Weissmann - Haifa, IL

International Classification:

G06F 9/48
G06F 9/30

Abstract:

In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

US Patent:

20200201671, Jun 25, 2020

Filed:

Dec 20, 2018

Appl. No.:

16/228136

Inventors:

- Santa Clara CA, US
RAJSHREE CHABUKSWAR - Sunnyvale CA, US
Russell Fenger - Beaverton OR, US
Shadi Khasawneh - Austin TX, US
Vijay Dhanraj - Beaverton OR, US
Mukund Ramakrishna - Austin TX, US
Atsuo Kuwahara - Portland OR, US
Eugene Gorbatov - Hillsboro OR, US
MONICA GUPTA - Santa Clara CA, US
CHRISTINE M. LIN - Sunnyvale CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/48
G06F 9/30
G06F 9/50

Abstract:

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

US Patent:

20190102221, Apr 4, 2019

Filed:

Sep 29, 2017

Appl. No.:

15/720296

Inventors:

- Santa Clara CA, US
Vijay Dhanraj - Beaverton OR, US
Russell J. Fenger - Beaverton OR, US
Vivek Garg - Folsom CA, US
Eugene Gorbatov - Hillsboro OR, US
Stephen H. Gunter - Beaverton OR, US
Monica Gupta - Hillsboro OR, US
Efraim Rotem - Haifa, IL
Krishnakanth V. Sistla - Beaverton OR, US
Guy M. Therien - Beaverton OR, US
Ankush Varma - Hillsboro OR, US
Eliezer Weissmann - Haifa, IL

International Classification:

G06F 9/48
G06F 9/30

Abstract:

In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

US Patent:

20190102227, Apr 4, 2019

Filed:

Sep 29, 2017

Appl. No.:

15/720222

Inventors:

- Santa Clara CA, US
Vijay Dhanraj - Beaverton OR, US
Russell Fenger - Beaverton OR, US
Vivek Garg - Folsom CA, US
Eugene Gorbatov - Hillsboro OR, US
Stephen Gunter - Beaverton OR, US
Monica Gupta - Hillsboro OR, US
Efraim Rotem - Haifa, IL
Krishnakanth Sistla - Beaverton OR, US
Guy Therien - Beaverton OR, US
Ankush Verma - Hillsboro OR, US
Eliezer Weissmann - Haifa, IL

International Classification:

G06F 9/50
G06F 9/48

Abstract:

In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

US Patent:

20170177415, Jun 22, 2017

Filed:

Dec 22, 2015

Appl. No.:

14/978182

Inventors:

- Santa Clara CA, US
Gaurav KHANNA - Hillsboro OR, US
Russell J. FENGER - Beaverton OR, US
Monica GUPTA - Hillsboro OR, US

International Classification:

G06F 9/50
G06F 9/455

Abstract:

Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.