Muhammad Farooq

US Patent:

20220342671, Oct 27, 2022

Filed:

Apr 27, 2021

Appl. No.:

17/241365

Inventors:

- Cambridge, GB
Muhammad Umar FAROOQ - Austin TX, US
Yasuo ISHII - Austin TX, US

International Classification:

G06F 9/38
G06F 9/32
G06F 9/30

Abstract:

Aspects of the present disclosure relate an apparatus comprising fetch circuitry and instruction storage circuitry. The fetch circuitry is to fetch instructions for execution by execution circuitry. The instruction storage circuitry is to store temporary copies of fetched instructions. The fetch circuitry is configured to preferentially fetch instructions from the instruction storage circuitry. The instruction storage circuitry is configured to, responsive to a storage condition being met, begin storing copies of consecutive fetched instructions, the storage condition indicating a utility of a current fetched instruction; and to, responsive to determining that a number of said stored consecutive instructions has reached a storage threshold, cease storing copies of subsequent fetched instructions.

US Patent:

20210271486, Sep 2, 2021

Filed:

Mar 2, 2020

Appl. No.:

16/806063

Inventors:

- Cambridge, GB
Joseph Michael PUSDESRIS - Austin TX, US
Muhammad Umar FAROOQ - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30
G06F 9/50

Abstract:

An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

US Patent:

20200310811, Oct 1, 2020

Filed:

Mar 26, 2019

Appl. No.:

16/364557

Inventors:

- Cambridge, GB
Muhammad Umar FAROOQ - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30
G06F 9/32

Abstract:

An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken. The target prediction storage comprises at least one entry that is configurable as a multi-taken entry to indicate that a source instruction flow changing instruction identified by that entry is a first instruction flow changing instruction with an associated first target address that identifies a series of instructions that is expected to exhibit static behaviour and that terminates with a second instruction flow changing instruction, where the second instruction flow changing instruction is unconditionally taken and has an associated second target address. The prediction circuitry is arranged, when making a prediction for a chosen instruction flow changing instruction that is identified by a multi-taken entry in the target prediction storage, to identify with reference to target address information stored in that multi-taken entry both the series of instructions and a target instruction at the second target address. It then causes the series of instructions and the target instruction to be identified in the fetch queue, and begins making further predictions starting from the target instruction at the second target address.

US Patent:

20200310812, Oct 1, 2020

Filed:

Mar 26, 2019

Appl. No.:

16/364570

Inventors:

- Cambridge, GB
Muhammad Umar FAROOQ - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken. During each prediction iteration, the prediction circuitry is arranged by default to access a prediction storage in order to produce prediction information for instructions associated with a specified block of instruction addresses (including at least the predict block being considered), and to use that prediction information to make the prediction for the predict block. Buffer storage is used to retain the prediction information obtained from the prediction storage during one or more previous prediction iterations, and detection circuitry is used to detect when a current predict block being considered during a current prediction iteration comprises one or more instruction addresses for which the associated prediction information is retained in the buffer storage. In that event, the above default behaviour is not adopted, and an override condition is triggered to cause the prediction information for those one or more instruction addresses to be obtained from the buffer storage rather than from the prediction storage, giving rise to a power saving.

US Patent:

20200110611, Apr 9, 2020

Filed:

Oct 9, 2018

Appl. No.:

16/155049

Inventors:

- Cambridge, GB
Muhammad Umar FAROOQ - Austin TX, US
Chris ABERNATHY - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

A data processing apparatus is provided that includes lookup circuitry to provide first prediction data in respect of a first block of instructions and second prediction data in respect of a second block of instructions. First processing circuitry provides a first control flow prediction in respect of the first block of instructions using the first prediction data and second processing circuitry provides a second control flow prediction in respect of the second block of instructions using the second prediction data. The first block of instructions and the second block of instructions collectively define a prediction block and the lookup circuitry uses a reference to the prediction block as at least part of an index to both the first prediction data and the second prediction data.

US Patent:

20200110615, Apr 9, 2020

Filed:

Oct 3, 2018

Appl. No.:

16/150372

Inventors:

- Cambridge, GB
Muhammad Umar FAROOQ - Austin TX, US
Chris ABERNATHY - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

A data processing apparatus is provided that includes global-history prediction circuitry that provides a prediction of an outcome of a given control flow instruction based on a result of execution of one or more previous control flow instructions. Correction circuitry provides a corrected prediction of the global-history prediction circuitry in respect of the given control flow instruction and cache circuitry, separate from the correction circuitry, stores the corrected prediction in respect of the given control flow instruction.

US Patent:

20200073666, Mar 5, 2020

Filed:

Sep 4, 2018

Appl. No.:

16/120674

Inventors:

- Cambridge, GB
Muhammad Umar FAROOQ - Austin TX, US
Chris ABERNATHY - Austin TX, US

International Classification:

G06F 9/38

Abstract:

Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction. The branch prediction circuitry stores a way prediction for which of the multiple ways contain the branch target predictions for a predicted next block of instructions and stores a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage. An active value of the flag suppresses the look-up in the main branch target storage for the predicted next block of instructions.

US Patent:

20180293166, Oct 11, 2018

Filed:

Apr 5, 2017

Appl. No.:

15/479348

Inventors:

- Cambridge, GB
Klas Magnus BRUCE - Leander TX, US
Vasu KUDARAVALLI - Austin TX, US
Adam GEORGE - Austin TX, US
Muhammad Umar FAROOQ - Austin TX, US
Joseph Michael PUSDESRIS - Austin TX, US

International Classification:

G06F 12/0811
G06F 12/0875
G06F 12/0891
G06F 12/0815
G06F 11/10

Abstract:

A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.