Muhammad Rehan Qureshi

US Patent:

8331129, Dec 11, 2012

Filed:

Sep 3, 2010

Appl. No.:

12/875423

Inventors:

Wei Yi - Mountain View CA, US
Frederick Perner - Santa Barbara CA, US
Matthew D. Pickett - San Francisco CA, US
Muhammad Shakeel Qureshi - Santa Clara CA, US

Assignee:

Hewlett-Packard Development Company, L. P. - Houston TX

International Classification:

G11C 11/00

US Classification:

365148, 365158

Abstract:

A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

US Patent:

20120236623, Sep 20, 2012

Filed:

Mar 17, 2011

Appl. No.:

13/050349

Inventors:

Muhammad Shakeel Qureshi - Santa Clara CA, US

International Classification:

G11C 11/00

US Classification:

365148

Abstract:

A memory device capable of being sensed with an oscillating signal includes a first terminal of a memristive element connected to an oscillating signal supply, and a second terminal of the memristive element connected to sensing circuitry, the sensing circuitry to determine an attenuation of an oscillating signal from the oscillating signal supply. A crossbar array includes a first set of parallel lines selectively connected to an oscillating signal supply, a second set of parallel lines intersecting the first set of parallel lines, the second set of parallel lines selectively connected to sensing circuitry, memristive memory elements being disposed at crosspoints between the first set of parallel lines and the second set of parallel lines, in which a memory controller of the crossbar array is to determine a resistive state of one of the memory elements by determining, with the sensing circuitry, an attenuation of an oscillating signal produced by the oscillating signal supply.

US Patent:

20130070534, Mar 21, 2013

Filed:

Apr 30, 2010

Appl. No.:

13/384885

Inventors:

Richard J. Carter - Los Altos CA, US
Muhammad Shakeel Qureshi - Santa Clara CA, US

International Classification:

G11C 7/10

US Classification:

36518905

Abstract:

A programmable current-limited voltage buffer - The programmable current-limited voltage buffer - includes at least one current-bias circuit - an inverter - a write-current set control circuit - and an adaptive current limiter - The inverter - is coupled to the current-bias circuit - and a reference-voltage source and is configured to couple a row line - to either the current-bias circuit - or the reference-voltage source in response to an input signal. The adaptive current limiter - is coupled to the current-bias circuit - and to the write-current set control circuit - and is configured to limit current flowing through the memory element - in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element - during switching in an array of memory elements.

US Patent:

20130223134, Aug 29, 2013

Filed:

Jan 31, 2011

Appl. No.:

13/884140

Inventors:

Wei Yi - Mountain View CA, US
Muhammad Chakeel Qureshi - Santa Barbara CA, US
Frederick Perner - Santa Barbara CA, US
Richard Carter - Los Altos CA, US

International Classification:

G11C 13/00

US Classification:

365148

Abstract:

A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.