Murat R Becer

US Patent:

7251797, Jul 31, 2007

Filed:

Nov 22, 2004

Appl. No.:

10/994858

Inventors:

Murat R. Becer - Cedar Park TX, US
Ilan Algor - Gnei-Tikva, IL
Amir Grinshpon - Tel Aviv, IL
Rafi Levy - Tel-Aviv, IL
Chanhee Oh - Austin TX, US
Rajendran V. Panda - Round Rock TX, US
Vladimir P. Zolotov - Putnam Valley NY, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 6, 716 2

Abstract:

Processes and systems () for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise () and path based delay noise () analysis. Effective delta delay determines an impact () on victim timing of an action by aggressors that occur during a region () where victim and aggressor timing windows overlap and determines an effective delta delay corresponding to any portion of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty () in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time , i. e. during a switching time window (a to a+u) () when uncertainty is included.

US Patent:

7594210, Sep 22, 2009

Filed:

Nov 16, 2006

Appl. No.:

11/560553

Inventors:

Murat R. Becer - Cedar Park TX, US
Joao M. Geada - Chelmsford MA, US
Isadore T. Katz - Harvard MA, US
Lee La France - Bolton MA, US

Assignee:

CLK Design Automation, Inc. - Littleton MA

International Classification:

G06F 17/50

US Classification:

716 6, 716 7, 703 16

Abstract:

A method includes grouping cells with similar topological characteristics into a family of cells, the topological characteristics being defined in part by topological layouts of transistors in the respective cells in the family of cells; and computing data characterizing a relationship between a variability of delay and a magnitude of delay shared among the cells in the family of cells.

US Patent:

7793243, Sep 7, 2010

Filed:

Dec 4, 2006

Appl. No.:

11/566543

Inventors:

Murat R. Becer - Cedar Park TX, US
Joao M. Geada - Chelmsford MA, US
Lee La France - Bolton MA, US
Nicholas Rethman - North Andover MA, US
Qian Shen - Shrewsbury MA, US

Assignee:

CLK Design Automation, Inc. - Littleton MA

International Classification:

G06F 17/50
G06F 17/30

US Classification:

716 6, 716 1, 716 4, 716 5, 716 7, 707 10

Abstract:

A system for circuit timing analysis includes a database for holding results of execution of portions of a timing analysis computation. Multiple computation modules are configured for concurrent execution of the portions of a timing analysis computation, for example, a static circuit timing analysis computation. A control subsystem is coupled to the database and to the computation modules, and is configured to receive results of the portions of the computation from the computation modules and to update the database using the received results. Based on the received results, the control module selects further portions of the computations for computation and assign each selected portion to one of the computation modules. The system makes use of parallel processing that is arranged in a way that avoids bottlenecks, such as at least some memory access bottlenecks resulting from data structure locking.

US Patent:

20040103386, May 27, 2004

Filed:

Nov 26, 2002

Appl. No.:

10/304423

Inventors:

Murat Becer - Round Rock TX, US
Ilan Algor - Ganei Tikva, IL
Rajendran Panda - Round Rock TX, US
David Blaauw - Ann Arbor MI, US

International Classification:

G06F017/50

US Classification:

716/013000, 716/012000, 716/014000

Abstract:

A method for designing and routing circuitry having reduced cross talk. Early noise analysis () is performed after global routing () but before detailed routing () in order to repair problems () before detailed routing () is performed. In one embodiment, the early noise analysis () is preceded by probabilistic extraction (). In one embodiment, probabilistic extraction () includes determining a probability of occurrence for each configuration in a predetermined set of configurations (). Probabilistic capacitance extraction is then performed (). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (). In one embodiment, probabilistic extraction () includes estimating aggressor strength () using the probabilistic distributed coupled RC network.

US Patent:

20210350059, Nov 11, 2021

Filed:

Jun 16, 2021

Appl. No.:

17/349568

Inventors:

- Canonsburg PA, US
Aveek SARKAR - Palo Alto CA, US
Altan ODABASI - Canonsburg PA, US
Scott JOHNSON - Canonsburg PA, US
Murat BECER - Canonsburg PA, US
William MULLEN - Canonsburg PA, US

International Classification:

G06F 30/367

Abstract:

A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of M, states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering Mcombinations. Related apparatus, systems, techniques and articles are also described.

US Patent:

20150379183, Dec 31, 2015

Filed:

Jun 8, 2015

Appl. No.:

14/733782

Inventors:

- San Jose CA, US
Murat Becer - Santa Clara CA, US
Mustafa Yazgan - Cupertino CA, US
Lei Yin - Santa Clara CA, US
John Lee - San Jose CA, US

International Classification:

G06F 17/50

Abstract:

Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.