Nader Vasseghi

US Patent:

46789405, Jul 7, 1987

Filed:

Jan 8, 1986

Appl. No.:

6/817228

Inventors:

Nader Vasseghi - Mountain View CA
Donald G. Goddard - Cupertino CA
Robert E. Eccles - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 1908
H03K 19003
H03K 1716
H03K 1756

US Classification:

307446

Abstract:

Output buffer circuits formed of merged bipolar transistor and CMOS transistors to produce either two output states or three output states includes a plurality of CMOS transistors and a pair of bipolar transistors. The output buffer circuits have high current drive capabilities and low propagation delay.

US Patent:

46124586, Sep 16, 1986

Filed:

Aug 28, 1985

Appl. No.:

6/770817

Inventors:

Nader Vasseghi - Mountain View CA
Donald G. Goddard - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 1908
H03K 19003
H03K 1716
H03K 1756

US Classification:

307446

Abstract:

Logic circuits formed of merged P-channel MOS transistors and bipolar transistors to produce a single logic gate include a plurality of P-channel MOS transistors and a pair of bipolar transistors. The logic gate circuits have low power dissipation and a large noise margin.

US Patent:

46058648, Aug 12, 1986

Filed:

Jan 4, 1985

Appl. No.:

6/688719

Inventors:

Hemmige D. Varadarajan - Sunnyvale CA
Nader Vasseghi - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19092
H03K 1901
H03K 1704
H03K 1760

US Classification:

307270

Abstract:

A line driver circuit is formed of a driver circuit section and a receiver circuit section. The driver circuit section provide a low impedance drive for charging and discharging quickly a capacitive load. A receiver circuit section includes an output level-shifting transistor which is adapted for translating a voltage at an output node of the driver circuit section to a compatible higher level.

US Patent:

47897970, Dec 6, 1988

Filed:

Jun 25, 1987

Appl. No.:

7/066915

Inventors:

Nader Vasseghi - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19003

US Classification:

307475

Abstract:

An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circuit (42), and a sensing circuit (26). The first bandgap generator (40) generates a first reference voltage (VB1) which has a positive temperature coefficient. The second bandgap generator (42) generates a second reference voltage (VB2) which has a negative temperature coefficient. A resultant base drive current (I. sub. x) is supplied to the base of a phase splitter transistor (Q2) in the output buffer (36). The resultant current (I. sub. x) is controlled by the first and second bandgap generators (40, 42), the current being higher at low temperatures and being smaller at high temperatures.