Nagashyamala R Dhanwada

US Patent:

7296251, Nov 13, 2007

Filed:

May 25, 2004

Appl. No.:

10/853370

Inventors:

Nagashyamala R. Dhanwada - Wappingers Falls NY, US
Youngsoo Shin - Millwood NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 9, 716 6, 716 7

Abstract:

Voltage islands enable a core-level power optimization of ASIC/SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

US Patent:

8234624, Jul 31, 2012

Filed:

Jan 25, 2007

Appl. No.:

11/626967

Inventors:

Robert J. Devins - Essex Junction VT, US
Nagashyamala R. Dhanwada - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44

US Classification:

717106, 717114, 717116, 717121, 703 13, 703 21, 703 22, 703 23, 716100, 716108, 716132

Abstract:

A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

US Patent:

20040111687, Jun 10, 2004

Filed:

Dec 4, 2002

Appl. No.:

10/309654

Inventors:

Nagashyamala Dhanwada - Wappingers Falls NY, US
Glenn Holmes - Wappingers Falls NY, US
Joseph Morrell - Wappingers Falls NY, US
Jose Luis Correia Neves - Poughkeepsie NY, US
Natesan Venkateswaran - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/45
G06F017/50

US Classification:

716/008000

Abstract:

An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic, and achieves it without loss of accuracy in the results. Annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data. The floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner. The abstraction based approach phases out by abstracting the leaf level logic (thus reducing the solution space of the floorplanner) and reintroducing them in the form of floorplan constraints (to account for the presence of the leaf level logic while determining the location of large blocks). The abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner. The overall concept of driving a floorplanning algorithm with a path based hyper-edge representation also helps to provide structural information about the netlist to the floorplanner.

US Patent:

20100268523, Oct 21, 2010

Filed:

Apr 20, 2009

Appl. No.:

12/426440

Inventors:

Nagashyamala R. Dhanwada - Fishkill NY, US
Joseph Arun - Bangalore, IN
William W. Dungan - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44

US Classification:

703 21

Abstract:

A method of generating system level power information for an embedded application configured to execute on a multi-core system-on-chip (SoC), which includes configuring a simulation model of hardware of the SoC that executes the embedded application; loading one or more software components of the embedded application into the simulation model of the SoC hardware; executing the one or more software components of the embedded application on the simulation model, and extracting state information about both the software components of the embedded application and hardware components of the SoC; determining, from the hardware state information, per-cycle energy values for the hardware components of the SoC; and creating a power profile from the software state information by accumulating the per-cycle energy values and assigning the per-cycle energy values to corresponding software components.

US Patent:

20200233933, Jul 23, 2020

Filed:

Jan 22, 2019

Appl. No.:

16/253812

Inventors:

- Armonk NY, US
Nagashyamala R. Dhanwada - Tenafly NJ, US
James Douglas Warnock - Somers NY, US

International Classification:

G06F 17/50

Abstract:

A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.