Namasivayam S Thangavelu

US Patent:

7089366, Aug 8, 2006

Filed:

Oct 8, 2003

Appl. No.:

10/682240

Inventors:

John W. Horrigan - Mountain View CA, US
Namasivayam Thangavelu - San Jose CA, US
George Vargese - Folsom CA, US
Brian Holscher - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/12
G06F 15/78

US Classification:

711135, 712 43, 710260

Abstract:

Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

US Patent:

7380063, May 27, 2008

Filed:

Jun 20, 2006

Appl. No.:

11/471773

Inventors:

John W. Horrigan - Mountain View CA, US
Namasivayam Thangavelu - San Jose CA, US
George Vargese - Folsom CA, US
Brian Holscher - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/12
G06F 1/32
G06F 13/24

US Classification:

711129, 711135, 710262, 713323, 713324

Abstract:

Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

US Patent:

6658532, Dec 2, 2003

Filed:

Dec 15, 1999

Appl. No.:

09/465216

Inventors:

John W. Horrigan - Mountain View CA
Namasivayam Thangavelu - San Jose CA
George Vargese - Folsom CA
Brian Holscher - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1212

US Classification:

711135

Abstract:

Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

US Patent:

20210158722, May 27, 2021

Filed:

Dec 4, 2020

Appl. No.:

17/112388

Inventors:

- Milpitas CA, US
Namasivayam THANGAVELU - San Jose CA, US

International Classification:

G09B 19/00
A61J 7/04
A61B 5/00

Abstract:

Various systems and methods for encouraging patient behavior utilize one or more sensors for gathering medical-related information about a patient and processing the medical-related information to provide feedback to the patient, such as notification reminders for dosing, testing, and/or other patient behaviors.