Nancy O Dillon

US Patent:

6963956, Nov 8, 2005

Filed:

Apr 2, 2004

Appl. No.:

10/817781

Inventors:

Richard M. Barth - Palo Alto CA, US
Ely K. Tsern - Los Altos CA, US
Mark A. Horowitz - Menlo Park CA, US
Donald C. Stark - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Frederick A. Ware - Los Altos Hills CA, US
Nancy David Dillon - Washington VA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F012/00

US Classification:

711154, 711101, 36518908, 36518903

Abstract:

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

US Patent:

8458426, Jun 4, 2013

Filed:

Jan 19, 2007

Appl. No.:

11/624966

Inventors:

Kevin Donnelly - Los Altos CA, US
Mark Johnson - Los Altos CA, US
Chanh Tran - San Jose CA, US
Nancy D. Dillon - Washington VA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711167, 711154, 711E12002, 710 25, 710 29, 710 45, 710106

Abstract:

In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

US Patent:

20020017929, Feb 14, 2002

Filed:

Jun 14, 2001

Appl. No.:

09/882420

Inventors:

Billy Garrett - Mountain View CA, US
John Dillon - Palo Alto CA, US
Michael Ching - Sunnyvale CA, US
William Stonecypher - San Jose CA, US
Andy Chan - San Jose CA, US
Matthew Griffin - Mountain View CA, US
Nancy Dillon - Marshall VA, US

International Classification:

H03L005/00

US Classification:

327/108000, 327/333000

Abstract:

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (), an analog voltage divider (), an input comparator (), a sampling latch (), a current control counter (), and a bitwise output driver (output driver A and output driver B ).

US Patent:

20020070771, Jun 13, 2002

Filed:

Sep 12, 2001

Appl. No.:

09/954561

Inventors:

Billy Garrett - Mountain View CA, US
John Dillon - Palo Alto CA, US
Michael Ching - Sunnyvale CA, US
William Stonecypher - San Jose CA, US
Andy Chan - San Jose CA, US
Matthew Griffin - Mountain View CA, US
Nancy Dillon - Marshall VA, US

International Classification:

H03B001/00

US Classification:

327/108000

Abstract:

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (), an analog voltage divider (), an input comparator (), a sampling latch (), a current control counter (), and a bitwise output driver (output driver A and output driver B ).

US Patent:

20020095560, Jul 18, 2002

Filed:

Jan 18, 2002

Appl. No.:

10/053632

Inventors:

Richard Barth - Palo Alto CA, US
Ely Tsern - Los Altos CA, US
Mark Horowitz - Menlo Park CA, US
Donald Stark - Los Altos CA, US
Craig Hampel - San Jose CA, US
Frederick Ware - Los Altos Hills CA, US
John Dillon - Palo Alto CA, US
Nancy Dillon - Washington VA, US

International Classification:

G06F012/00

US Classification:

711/169000, 711/105000

Abstract:

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

US Patent:

20020196059, Dec 26, 2002

Filed:

Aug 29, 2002

Appl. No.:

10/230931

Inventors:

Billy Garrett - Mountain View CA, US
John Dillon - Palo Alto CA, US
Michael Ching - Sunnyvale CA, US
William Stonecypher - San Jose CA, US
Andy Chan - San Jose CA, US
Matthew Griffin - Mountain View CA, US
Nancy Dillon - Marshall VA, US

International Classification:

H03B001/00

US Classification:

327/108000

Abstract:

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (), an analog voltage divider (), an input comparator (), a sampling latch (), a current control counter (), and a bitwise output driver (output driver A and output driver B ).

US Patent:

20050040878, Feb 24, 2005

Filed:

Jul 14, 2004

Appl. No.:

10/890972

Inventors:

Billy Garrett - Mountain View CA, US
John Dillon - Palo Alto CA, US
Nancy Dillon - Marshall VA, US
Michael Ching - Sunnyvale CA, US
William Stonecypher - San Jose CA, US
Andy Chan - San Jose CA, US
Matthew Griffin - Mountain View CA, US

International Classification:

H03L005/00

US Classification:

327333000

Abstract:

A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.

US Patent:

20050083104, Apr 21, 2005

Filed:

Nov 5, 2004

Appl. No.:

10/981808

Inventors:

Billy Garrett - Mountain View CA, US
John Dillon - Palo Alto CA, US
Michael Ching - Sunnyvale CA, US
Andy Chan - San Jose CA, US
Matthew Griffin - Mountain View CA, US
Nancy Dillon - Marshall VA, US

International Classification:

H03B001/00

US Classification:

327333000

Abstract:

A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.