Nancy A Greco

US Patent:

6335151, Jan 1, 2002

Filed:

Jun 18, 1999

Appl. No.:

09/335609

Inventors:

Christopher P. Ausschnitt - Brookfield CT
Nancy Greco - Lagrangeville NY
Ernest N. Levine - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 900

US Classification:

430322, 430 5

Abstract:

A lithographic process for creation and replication of well-controlled surfaces of arbitrary profiles on a sub-micron scale. The surfaces are defined by a mathematical function using a binary mask, consisting partly or wholly of subresolution features, and a photoresist film of pre-specified absorption and thickness. The process comprises the steps of (a) creating a mask, (b) imaging the mask pattern on an absorbing photoresist film to a predetermined thickness, and (c) transferring the three dimensional surface to a substrate.

US Patent:

6339022, Jan 15, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/475712

Inventors:

Arne W. Ballantine - Coldspring NY
Cheryl G. Faltermeier - Lagrange NY
Jeffrey D. Gilbert - Burlington VT
Ronald D. Goldblatt - Yorktown Heights NY
Nancy A. Greco - Lagrangeville NY
Stephen E. Greco - Lagrangeville NY
Frank V. Liucci - Wappingers Falls NY
Glenn Robert Miller - Essex Junction VT
Bruce A. Root - Westford VT
Andrew H. Simon - Fishkill NY
Anthony K. Stamper - Williston VT
Ronald A. Warren - Essex Junction VT
David H. Yao - Essex VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438660, 438663, 438687

Abstract:

A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

US Patent:

6635527, Oct 21, 2003

Filed:

May 26, 1999

Appl. No.:

09/318867

Inventors:

Nancy Anne Greco - Lagrangeville NY
David Louis Harame - Mohegan Lake NY
Gary Robert Hueckel - Putnam Valley NY
Joseph Thomas Kocis - Pleasant Valley NY
Dominique Nguyen Ngoc - Peekskill NY
Kenneth Jay Stein - Sandy Hook CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218242

US Classification:

438250, 438238, 438239, 438393

Abstract:

An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

US Patent:

6927440, Aug 9, 2005

Filed:

Sep 9, 2003

Appl. No.:

10/658036

Inventors:

Nancy Anne Greco - Lagrangeville NY, US
David Louis Harame - Mohegan Lake NY, US
Gary Robert Hueckel - Putnam Valley NY, US
Joseph Thomas Kocis - Pleasant Valley NY, US
Dominique Nguyen Ngoc - Lake Peeskill NY, US
Kenneth Jay Stein - Sandy Hook CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L027/108
H01L029/41

US Classification:

257296, 257532

Abstract:

An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

US Patent:

7300825, Nov 27, 2007

Filed:

Apr 30, 2004

Appl. No.:

10/835953

Inventors:

Nancy Anne Greco - Lagrangeville NY, US
Stephen Edward Greco - Lagrangeville NY, US
Erik L. Hedberg - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438130, 438585, 257209, 257E21579

Abstract:

Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.

US Patent:

7408206, Aug 5, 2008

Filed:

Nov 21, 2005

Appl. No.:

11/164377

Inventors:

Kenneth L. DeVries - Hopewell Junction NY, US
Nancy Anne Greco - LaGrangeville NY, US
Joan Preston - Wimberley TX, US
Stephen Larry Runyon - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/017

US Classification:

257127, 257170, 257409, 257452, 257484, 257605, 257E29012

Abstract:

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

US Patent:

7480990, Jan 27, 2009

Filed:

Jan 6, 2006

Appl. No.:

11/306668

Inventors:

John A. Fitzsimmons - Poughkeepsie NY, US
William J. Cote - Poughquag NY, US
Nancy A. Greco - LaGrangeville NY, US
Thomas H. Ivers - Hopewell Junction NY, US
Steven Moskowitz - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 3/02
H01L 21/302

US Classification:

29846, 29825, 29852, 438689, 438745

Abstract:

Methods for forming conductor contacts provide for etching through a capping layer located upon a conductor contact region within a substrate. A first pair of methods provide for etching through at least a lower thickness of the capping layer with other than a reactive ion etch to provide an exposed conductor contact region. A partially overlapping second pair of methods provides for converting at least an upper thickness of the capping layer to a converted material layer that is removed incident to providing an exposed conductor contact region. As adjunct to any of the methods, a liner layer is formed and located upon the exposed conductor contact region in absence of an undesirable reactive environment.

US Patent:

7759173, Jul 20, 2010

Filed:

Apr 15, 2008

Appl. No.:

12/103212

Inventors:

Kenneth L. DeVries - Hopewell Junction NY, US
Nancy Anne Greco - Lagrangeville NY, US
Joan Preston - Wimberley TX, US
Stephen Larry Runyon - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/332

US Classification:

438140, 438381, 257127, 257170

Abstract:

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.