Nancy Eileen Morton

US Patent:

50200593, May 28, 1991

Filed:

Mar 31, 1989

Appl. No.:

7/331411

Inventors:

Allen L. Gorin - Fair Lawn NJ
Patrick A. Makofsky - Randolph NJ
Nancy Morton - Dover NJ
Neal C. Oliver - Madison NJ
Richard R. Shively - Convent Station NJ
Christopher A. Stanziola - Hyde Park NY

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G06F 1118

US Classification:

371 113

Abstract:

An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4. times. 4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs.