Nancy Ann Pratt

US Patent:

7317348, Jan 8, 2008

Filed:

Jan 27, 2006

Appl. No.:

11/275773

Inventors:

Nancy H. Pratt - Essex Junction VT, US
Sebastian Theodore Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 5/00

US Classification:

327551, 327105

Abstract:

A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

US Patent:

7463083, Dec 9, 2008

Filed:

Nov 9, 2007

Appl. No.:

11/937559

Inventors:

Nancy H. Pratt - Essex Junction VT, US
Sebastian Theodore Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 5/00

US Classification:

327551, 327105

Abstract:

A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

US Patent:

7765351, Jul 27, 2010

Filed:

Mar 12, 2007

Appl. No.:

11/684687

Inventors:

Pascal A. Nsame - Colchester VT, US
Anthony D. Polson - Jericho VT, US
Nancy H. Pratt - Essex Junction VT, US
Sebastian T. Ventrone - Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

710244, 710260, 710240, 710200, 711170

Abstract:

A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

US Patent:

7873961, Jan 18, 2011

Filed:

Jul 29, 2005

Appl. No.:

11/161330

Inventors:

Laura F Miller - Essex Junction VT, US
Nancy H. Pratt - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 15/00
G06F 12/00

US Classification:

718100, 718107, 718108, 712208, 712228, 711173, 711207, 711208

Abstract:

A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

US Patent:

8037337, Oct 11, 2011

Filed:

Nov 28, 2007

Appl. No.:

11/946096

Inventors:

Nancy H. Pratt - Essex Junction VT, US
Sebastian Theodore Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04

US Classification:

713500

Abstract:

A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

US Patent:

20050096862, May 5, 2005

Filed:

Nov 4, 2003

Appl. No.:

10/605884

Inventors:

Jason Norman - South Burlington VT, US
Nancy Pratt - Essex Junction VT, US
Sebastian Ventrone - South Burlington VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R031/14

US Classification:

702117000

Abstract:

A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.

US Patent:

20070288787, Dec 13, 2007

Filed:

Aug 10, 2007

Appl. No.:

11/836827

Inventors:

Nancy Pratt - Essex Junction VT, US
Sebastian Ventrone - South Burlington VT, US

International Classification:

G06F 1/00

US Classification:

713500000

Abstract:

A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

US Patent:

20070294519, Dec 20, 2007

Filed:

Jun 19, 2006

Appl. No.:

11/424943

Inventors:

Laura F. Miller - Essex Junction VT, US
Pascal A. Nsame - Colchester VT, US
Nancy H. Pratt - Essex Junction VT, US
Sebastian T. Ventrone - S. Burlington VT, US

International Classification:

G06F 9/44

US Classification:

712241

Abstract:

An integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.