Naomi D Yoshida

US Patent:

7119571, Oct 10, 2006

Filed:

Nov 24, 2004

Appl. No.:

10/997267

Inventors:

Naomi Yoshida - Sunnyvale CA, US
Toshiyuki Nagata - Los Gatos CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G01R 31/26

US Classification:

324765

Abstract:

A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

US Patent:

7365529, Apr 29, 2008

Filed:

Aug 18, 2006

Appl. No.:

11/465646

Inventors:

Naomi Yoshida - Sunnyvale CA, US
Toshiyuki Nagata - Los Gatos CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G01R 31/28

US Classification:

3241581

Abstract:

A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

US Patent:

8227352, Jul 24, 2012

Filed:

Apr 25, 2011

Appl. No.:

13/093679

Inventors:

Hang Yu - Woodland CA, US
Deenesh Padhi - Sunnyvale CA, US
Man-Ping Cai - Saratoga CA, US
Naomi Yoshida - Sunnyvale CA, US
Li Yan Miao - San Francisco CA, US
Siu F. Cheng - Los Angeles CA, US
Shahid Shaikh - Santa Clara CA, US
Sohyun Park - Fremont CA, US
Heung Lak Park - Santa Clara CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/308
H01L 21/32

US Classification:

438703, 438761, 257E21258, 257E21231

Abstract:

Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer.

US Patent:

8349741, Jan 8, 2013

Filed:

Apr 25, 2012

Appl. No.:

13/455916

Inventors:

Hang Yu - Woodland CA, US
Deenesh Padhi - Sunnyvale CA, US
Man-Ping Cai - Saratoga CA, US
Naomi Yoshida - Sunnyvale CA, US
Li Yan Miao - San Francisco CA, US
Siu F. Cheng - Los Angeles CA, US
Shahid Shaikh - Santa Clara CA, US
Sohyun Park - Fremont CA, US
Heung Lak Park - Santa Clara CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/308
H01L 21/32

US Classification:

438703, 438761, 257E21258, 257E21231

Abstract:

Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less, and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater.

US Patent:

20230025937, Jan 26, 2023

Filed:

Sep 29, 2022

Appl. No.:

17/955996

Inventors:

- Santa Clara CA, US
Wei V. Tang - Santa Clara CA, US
Seshadri Ganguli - Sunnyvale CA, US
Sang Ho Yu - Cupertino CA, US
Feng Q. Liu - San Jose CA, US
Jeffrey W. Anthis - San Jose CA, US
David Thompson - San Jose CA, US
Jacqueline S. Wrench - San Jose CA, US
Naomi Yoshida - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/285
C23C 16/455
C23C 16/18
H01L 23/532
C23C 16/04

Abstract:

Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200 C. by using an organic platinum group metal precursor.

US Patent:

20210384035, Dec 9, 2021

Filed:

Apr 8, 2021

Appl. No.:

17/225667

Inventors:

- Santa Clara CA, US
Shih Chung Chen - Cupertino CA, US
Kedi Wu - Fremont CA, US
Ashley Lin - New Taipei, TW
Chi-Chou Lin - San Jose CA, US
Yi Xu - San Jose CA, US
Yu Lei - Belmont CA, US
Mandyam Sriram - San Jose CA, US
Wen Ting Chen - San Jose CA, US
Srinivas Gandikota - Santa Clara CA, US
Chenfei Shen - San Jose CA, US
Naomi Yoshida - Sunnyvale CA, US
He Ren - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/285
H01L 21/02
C23C 16/14
C23C 16/02

Abstract:

Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a fluorine-free metallic tungsten film. The fluorine-free metallic tungsten film is exposed to a second process condition to deposit a tungsten film on the fluorine-free metallic tungsten film.

US Patent:

20210384036, Dec 9, 2021

Filed:

Jun 4, 2021

Appl. No.:

17/339454

Inventors:

- Santa Clara CA, US
Chi-Chou Lin - San Jose CA, US
Kedi Wu - Fremont CA, US
Wen Ting Chen - San Jose CA, US
Shih Chung Chen - Cupertino CA, US
Srinivas Gandikota - Santa Clara CA, US
Mandyam Sriram - San Jose CA, US
Chenfei Shen - San Jose CA, US
Naomi Yoshida - Sunnyvale CA, US
He Ren - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/285
C23C 16/455
C23C 16/14
C23C 16/04

Abstract:

Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.

US Patent:

20210317580, Oct 14, 2021

Filed:

Apr 14, 2020

Appl. No.:

16/848784

Inventors:

- Santa Clara CA, US
He REN - San Jose CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Nikolaos BEKIARIS - Campbell CA, US
Mehul NAIK - San Jose CA, US
Martin Jay SEAMONS - San Jose CA, US
Jingmei LIANG - Santa Clara CA, US
Mei-Yee SHEK - Santa Clara CA, US

International Classification:

C23C 16/56
H01L 21/768

Abstract:

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material