Naomi Yoshida from 1890 Sutter St, San Francisco, CA 94115, Phone: 4155670366

Resumes

Senior Business Analyst

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Location:

Santa Clara, CA

Industry:

Semiconductors

Work:

Renesas Electronics Corporation Oct 2008 - Apr 2011
Data Management and Business Specialist
Renesas Electronics Corporation Oct 2008 - Apr 2011
Senior Business Analyst
Hitachi Transport System Feb 2004 - Sep 2008
Business Consultant
Hitachi 1999 - 2004
Corporate Planning Manager

Education:

University of California, Berkeley 2001 - 2002
The University of Dallas 1978 - 1981

Skills:

Sap
Business Intelligence
Management
Training
Business Proces Reengineering
Data Modeling
Business Analysis
Expatriate Management
Transfer Pricing
Supply Chain Management
System Integrators

Languages:

Japanese

Director, Distinguished Member Of Technical Staff

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Location:

Santa Clara, CA

Industry:

Semiconductors

Work:

Applied Materials
Director, Distinguished Member of Technical Staff
Applied Materials 2007 - 2012
Senior Member of Technical Staff
Applied Materials 2003 - 2007
Member of Technical Staff
Applied Materials 2002 - 2003
Technology
Applied Materials 2000 - 2002
Key Account Technologist

Education:

International Christian University 1992 - 1994
Master of Science, Masters, Physics

Skills:

Thin Films
Semiconductors
Semiconductor Industry
Failure Analysis
Silicon
Cvd
Product Engineering
Characterization
Cmos
Spc
Materials Science
Engineering Management
Pvd
Ic
Pecvd
Nanotechnology
Metrology
Design of Experiments
Process Integration
Electrical Testing
Reliability Test
Electroplating

Languages:

English
Japanese

Naomi Yoshida

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Skills:

Microsoft Office
Customer Service
Windows
Microsoft Word
Outlook
Microsoft Excel
Powerpoint
English
Research
Leadership
Sales
Public Speaking
Social Media
Strategic Planning

Naomi Yoshida

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Naomi Yoshida

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Naomi Yoshida

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Location:

United States

Us Patents

Test Structure Design For Reliability Test
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US Patent:

7119571, Oct 10, 2006
Filed:

Nov 24, 2004
Appl. No.:

10/997267
Inventors:

Naomi Yoshida - Sunnyvale CA, US
Toshiyuki Nagata - Los Gatos CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

G01R 31/26
US Classification:

324765
Abstract:

A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

Test Structure Design For Reliability Test
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US Patent:

7365529, Apr 29, 2008
Filed:

Aug 18, 2006
Appl. No.:

11/465646
Inventors:

Naomi Yoshida - Sunnyvale CA, US
Toshiyuki Nagata - Los Gatos CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

G01R 31/28
US Classification:

3241581
Abstract:

A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

Oxygen Free Deposition Of Platinum Group Metal Films
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US Patent:

20230025937, Jan 26, 2023
Filed:

Sep 29, 2022
Appl. No.:

17/955996
Inventors:

- Santa Clara CA, US
Wei V. Tang - Santa Clara CA, US
Seshadri Ganguli - Sunnyvale CA, US
Sang Ho Yu - Cupertino CA, US
Feng Q. Liu - San Jose CA, US
Jeffrey W. Anthis - San Jose CA, US
David Thompson - San Jose CA, US
Jacqueline S. Wrench - San Jose CA, US
Naomi Yoshida - Sunnyvale CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 21/285
C23C 16/455
C23C 16/18
H01L 23/532
C23C 16/04
Abstract:

Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200 C. by using an organic platinum group metal precursor.

Fluorine-Free Tungsten Ald And Tungsten Selective Cvd For Dielectrics
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US Patent:

20210384035, Dec 9, 2021
Filed:

Apr 8, 2021
Appl. No.:

17/225667
Inventors:

- Santa Clara CA, US
Shih Chung Chen - Cupertino CA, US
Kedi Wu - Fremont CA, US
Ashley Lin - New Taipei, TW
Chi-Chou Lin - San Jose CA, US
Yi Xu - San Jose CA, US
Yu Lei - Belmont CA, US
Mandyam Sriram - San Jose CA, US
Wen Ting Chen - San Jose CA, US
Srinivas Gandikota - Santa Clara CA, US
Chenfei Shen - San Jose CA, US
Naomi Yoshida - Sunnyvale CA, US
He Ren - San Jose CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 21/285
H01L 21/02
C23C 16/14
C23C 16/02
Abstract:

Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a fluorine-free metallic tungsten film. The fluorine-free metallic tungsten film is exposed to a second process condition to deposit a tungsten film on the fluorine-free metallic tungsten film.

Fluorine-Free Tungsten Ald For Dielectric Selectivity Improvement
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US Patent:

20210384036, Dec 9, 2021
Filed:

Jun 4, 2021
Appl. No.:

17/339454
Inventors:

- Santa Clara CA, US
Chi-Chou Lin - San Jose CA, US
Kedi Wu - Fremont CA, US
Wen Ting Chen - San Jose CA, US
Shih Chung Chen - Cupertino CA, US
Srinivas Gandikota - Santa Clara CA, US
Mandyam Sriram - San Jose CA, US
Chenfei Shen - San Jose CA, US
Naomi Yoshida - Sunnyvale CA, US
He Ren - San Jose CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 21/285
C23C 16/455
C23C 16/14
C23C 16/04
Abstract:

Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.

Method Of Dielectric Material Fill And Treatment
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US Patent:

20210317580, Oct 14, 2021
Filed:

Apr 14, 2020
Appl. No.:

16/848784
Inventors:

- Santa Clara CA, US
He REN - San Jose CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Nikolaos BEKIARIS - Campbell CA, US
Mehul NAIK - San Jose CA, US
Martin Jay SEAMONS - San Jose CA, US
Jingmei LIANG - Santa Clara CA, US
Mei-Yee SHEK - Santa Clara CA, US
International Classification:

C23C 16/56
H01L 21/768
Abstract:

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

Horizontal Gate All Around Device Nanowire Air Gap Spacer Formation
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US Patent:

20200411656, Dec 31, 2020
Filed:

Sep 14, 2020
Appl. No.:

17/020372
Inventors:

- Santa Clara CA, US
Nam Sung KIM - Sunnyvale CA, US
Bingxi Sun WOOD - Cupertino CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Sheng-Chin KUNG - Milpitas CA, US
Miao JIN - San Jose CA, US
International Classification:

H01L 29/423
H01L 29/78
H01L 21/02
H01L 29/775
H01L 29/786
H01L 29/06
H01L 29/66
Abstract:

Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.

Integrated Dipole Flow For Transistor
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US Patent:

20200373404, Nov 26, 2020
Filed:

May 18, 2020
Appl. No.:

16/876276
Inventors:

- Santa Clara CA, US
Karla M. Bernal Ramos - San Jose CA, US
Luping Li - Santa Clara CA, US
Shih Chung Chen - Cupertino CA, US
Jacqueline S. Wrench - San Jose CA, US
Yixiong Yang - Fremont CA, US
Steven C.H. Hung - Sunnyvale CA, US
Srinivas Gandikota - Santa Clara CA, US
Naomi Yoshida - Sunnyvale CA, US
Lin Dong - San Jose CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 29/51
H01L 29/40
Abstract:

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitriride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).