Natalia L Lavrovskaya

US Patent:

7719048, May 18, 2010

Filed:

Apr 26, 2007

Appl. No.:

11/796050

Inventors:

Jeff A. Babcock - Sunnyvale CA, US
Yuri Mirgorodski - Sunnyvale CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/336

US Classification:

257316, 257E27103

Abstract:

A heating element is utilized to improve the bias conditions of an EPROM cell during program and erase operations. The heating element can also be used to anneal or condition the cell for improved charge storage. During a program or an erase operation, the cell's control gate and read transistor are set to ground. The heating element then has a voltage potential applied across its terminals, causing current to flow in this resistor. As the current density increases, the resistor begins to generate heat. This heat is thermally coupled into the cell's floating gate, causing its temperature to rise.

US Patent:

7919805, Apr 5, 2011

Filed:

May 25, 2007

Appl. No.:

11/807322

Inventors:

Yuri Mirgorodski - Sunnyvale CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 29/76

US Classification:

257314, 257E293, 438201

Abstract:

In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a lightly doped region or a deep trench isolation region.

US Patent:

7919807, Apr 5, 2011

Filed:

Mar 29, 2007

Appl. No.:

11/729710

Inventors:

Jeffrey A. Babcock - Sunnyvale CA, US
Yuri Mirgorodski - Sunnyvale CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 29/788
H01L 29/792

US Classification:

257315, 257316, 257324

Abstract:

The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.

US Patent:

8183621, May 22, 2012

Filed:

Feb 28, 2011

Appl. No.:

13/037199

Inventors:

Jeffrey A. Babcock - Sunnyvale CA, US
Yuri Mirgorodski - Sunnyvale CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/788
H01L 29/792

US Classification:

257318, 257315, 257316, 257324

Abstract:

The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.

US Patent:

8247862, Aug 21, 2012

Filed:

Mar 2, 2010

Appl. No.:

12/716101

Inventors:

Jeff A Babcock - Sunnyvale CA, US
Yuri Mirgorodski - Sunnyvale CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 16/04

US Classification:

257321, 257316, 257318, 257319, 257E2168, 257E21681, 257E21683, 36518501

Abstract:

A method is provided for enhancing charge storage in an EPROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.

US Patent:

20100032731, Feb 11, 2010

Filed:

Jul 6, 2009

Appl. No.:

12/498141

Inventors:

Jeffrey A. Babcock - Santa Clara CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US
Alexei Sadovnikov - San Jose CA, US

International Classification:

H01L 29/80

US Classification:

257280, 257E2931

Abstract:

In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.

US Patent:

20120230118, Sep 13, 2012

Filed:

May 21, 2012

Appl. No.:

13/477019

Inventors:

Jeffrey A. Babcock - Sunnyvale CA, US
Yuri Mirgorodski - Sunnyvale CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G11C 16/10

US Classification:

36518529

Abstract:

The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.

US Patent:

7425741, Sep 16, 2008

Filed:

Jul 21, 2005

Appl. No.:

11/186442

Inventors:

Andrew Strachan - Santa Clara CA, US
Natalia Lavrovskaya - Sunnyvale CA, US
Saurabh Desai - Fremont CA, US
Roozbeh Parsa - San Jose CA, US
Yuri Mirgorodski - Sunnyvale CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 29/788

US Classification:

257315, 257316, 257E293

Abstract:

A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer in the fabrication process flow, but any biased conductive layer can be used.