Nathan Fox Hanagami

US Patent:

20060262938, Nov 23, 2006

Filed:

May 18, 2005

Appl. No.:

11/131913

Inventors:

Daniel Gauger - Cambridge MA, US
Christopher Ickler - Sudbury MA, US
Nathan Hanagami - Framingham MA, US
Edwin Johnson - Ashland MA, US

International Classification:

H04R 29/00

US Classification:

381056000

Abstract:

Adapting an audio response addresses perceptual effects of an interfering signal, such as of a residual ambient noise or other interference in an earpiece of a headphone. In one aspect, an input audio signal is presented substantially unmodified when it is at levels substantially above the interfering signal and is compressed when at or below the level of the interfering signal. The approach can make use of a measured level of an acoustic signal, for example, within an earpiece of a headset, and use the measured level in conjunction with the level of an input audio signal to determine compression characteristics without requiring separation of an interfering signal present in the monitored acoustic signal from a component related to the input audio signal. In another aspect, presentation characteristics of an input audio signal are determined to reduce distraction from an interfering signal, such as from a background conversation.

US Patent:

20210089068, Mar 25, 2021

Filed:

Sep 25, 2019

Appl. No.:

16/583008

Inventors:

- Cupertino CA, US
Jay B. Fletcher - Sunnyvale CA, US
Nathan F. Hanagami - San Francisco CA, US

International Classification:

G05F 1/575
G05F 1/59

Abstract:

A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.