Nathan S Nunamaker from 1714 Magnolia Oak Pl, Durham, NC 27703, Phone: 9195964726

Use Of Register Renaming System For Forwarding Intermediate Results Between Constituent Instructions Of An Expanded Instruction
view source
US Patent:

7669039, Feb 23, 2010
Filed:

Jan 24, 2007
Appl. No.:

11/626424
Inventors:

Michael Scott McIlvaine - Raleigh NC, US
James Norris Dieffenderfer - Apex NC, US
Nathan Samuel Nunamaker - Durham NC, US
Thomas Andrew Sartorius - Raleigh NC, US
Rodney Wayne Smith - Raleigh NC, US
Assignee:

QUALCOMM Incorporated - San Diego
International Classification:

G06F 9/345
US Classification:

712217
Abstract:

Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs a look up in the constituent instruction rename table and reads the intermediate results from the physical register. Constituent instruction rename logic tracks the constituent instructions through the pipeline, and delete the constituent instruction rename table entry and returns the PRN to a free list when the second constituent instruction has read the intermediate results.

Method And Apparatus For Avoiding Data Dependency Hazards In A Microprocessor Pipeline Architecture Using A Multi-Bit Age Vector
view source
US Patent:

7730282, Jun 1, 2010
Filed:

Aug 11, 2004
Appl. No.:

10/916188
Inventors:

James N. Dieffenderfer - Apex NC, US
Nathan S. Nunamaker - Durham NC, US
Sanjay B. Patel - Cary NC, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 9/00
US Classification:

712216, 712217
Abstract:

A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.

System And Method For Executing Instructions Prior To An Execution Stage In A Processor
view source
US Patent:

8127114, Feb 28, 2012
Filed:

Mar 28, 2007
Appl. No.:

11/692685
Inventors:

Kiran Ravi Seth - Morrisville NC, US
James Norris Dieffenderfer - Apex NC, US
Michael Scott McIlvaine - Raleigh NC, US
Nathan Samuel Nunamaker - Durham NC, US
Assignee:

QUALCOMM Incorporated - San Diego CA
International Classification:

G06F 9/30
US Classification:

712214
Abstract:

A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly executing the instruction prior to the execution stage in the pipeline speeds up the execution of the instruction and allows the processor to more effectively utilize its resources, thus increasing the processor's efficiency.

Digital Data Processing Apparatus Having Multi-Level Register File
view source
US Patent:

20050289299, Dec 29, 2005
Filed:

Jun 24, 2004
Appl. No.:

10/875373
Inventors:

Nathan Nunamaker - Durham NC, US
Jack Randolph - Rochester MN, US
Kenichi Tsuchiya - Cary NC, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F012/00
US Classification:

711122000, 712219000
Abstract:

A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

Digital Data Processing Apparatus Having Multi-Level Register File
view source
US Patent:

20080022044, Jan 24, 2008
Filed:

Aug 8, 2007
Appl. No.:

11/835519
Inventors:

Nathan Nunamaker - Durham NC, US
Jack Randolph - Rochester MN, US
Kenichi Tsuchiya - Cary NC, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

G06F 12/00
US Classification:

711122000
Abstract:

A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Selection logic enables selecting output of either register bank for input to processor execution logic. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

Write-Through-Read (Wtr) Comparator Circuits, Systems, And Methods Employing Write-Back Stage And Use Of Same With A Multiple-Port File
view source
US Patent:

20110197021, Aug 11, 2011
Filed:

Feb 10, 2010
Appl. No.:

12/703342
Inventors:

Gregory Christopher Burda - Raleigh NC, US
Michael Scott McIlvaine - Raleigh NC, US
Nathan Samuel Nunamaker - Raleigh NC, US
Yeshwant Nagaraj Kolla - Raleigh NC, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 12/00
US Classification:

711108, 711149, 711E12001
Abstract:

Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.