Nathan D Tuck

US Patent:

6597363, Jul 22, 2003

Filed:

Aug 20, 1999

Appl. No.:

09/378637

Inventors:

Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 120

US Classification:

345506, 345545, 345563, 345653, 345654

Abstract:

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

US Patent:

6717576, Apr 6, 2004

Filed:

Aug 20, 1999

Appl. No.:

09/377503

Inventors:

Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA
Shun Wai Go - Milpitas CA
Lindy Fung - Sunnyvale CA
Tuan D. Nguyen - San Jose CA
Joseph P. Grass - Menlo Park CA
Bo Hong - San Jose CA
Abraham Mammen - Pleasanton CA
Abbas Rashid - Fremont CA
Albert Suan-Wei Tsay - Fremont CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 1500

US Classification:

345419, 345506, 345522

Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

US Patent:

6771264, Aug 3, 2004

Filed:

Dec 17, 1999

Appl. No.:

09/213990

Inventors:

Jerome F. Duluk - Palo Alto CA
Stephen L. Dodgen - Boulder Creek CA
Joseph P. Bratt - San Jose CA
Matthew Papakipos - Menlo Park CA
Nathan Tuck - San Diego CA
Richard E. Hessel - Pleasanton CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 1560

US Classification:

345426, 345584

Abstract:

A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (v , v , n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor.

US Patent:

7167181, Jan 23, 2007

Filed:

Jun 9, 2003

Appl. No.:

10/458493

Inventors:

Richard E. Hessel - Pleasanton CA, US
Vaughn T. Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph P. Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen L. Dodgen - Boulder Creek CA, US
Emerson S. Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Y. Ho - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew N. Papakipos - Menlo Park CA, US
Jason R. Redgrave - Mountain View CA, US
Sushma S. Trivedi - Sunnyvale CA, US
Nathan D. Tuck - San Diego CA, US
Shun Wai Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan D. Nguyen - San Jose CA, US
Joseph P. Grass - Menlo Park CA, US
Bo Hong - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Suan-Wei Tsay - Fremont CA, US

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 1/20
G06T 15/40
G09G 5/00

US Classification:

345506, 345421, 345613, 345614

Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

US Patent:

7543119, Jun 2, 2009

Filed:

Feb 10, 2006

Appl. No.:

11/352192

Inventors:

Richard Edward Hessel - Pleasanton CA, US
Nathan Daniel Tuck - Boulder CO, US
Korbin S. Van Dyke - Sunol CA, US
Chetana N. Keltcher - Sunnyvale CA, US

International Classification:

G06F 12/00

US Classification:

711154, 712 2

Abstract:

A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.

US Patent:

7808503, Oct 5, 2010

Filed:

Dec 19, 2006

Appl. No.:

11/613093

Inventors:

Richard E. Hessel - Pleasanton CA, US
Vaughn T. Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph P. Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen L. Dodgen - Boulder Creek CA, US
Emerson S. Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Y. Yo - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew N. Papakipos - Menlo Park CA, US
Jason R. Redgrave - Mountain View CA, US
Sushma S. Trivedi - Sunnyvale CA, US
Nathan D. Tuck - San Diego CA, US
Shun Wai Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan D. Nguyen - San Jose CA, US
Joseph P. Grass - Menlo Park CA, US
Bo Hong - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Suan-Wei Tsay - Fremont CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06T 1/20
G06T 15/00
G06T 15/10

US Classification:

345506, 345419, 345427

Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

US Patent:

8356144, Jan 15, 2013

Filed:

May 29, 2009

Appl. No.:

12/475393

Inventors:

Richard Hessel - Pleasanton CA, US
Chetana N. Keltcher - Lexington MA, US
Nathan Daniel Tuck - Corvallis OR, US
Korbin S. Van Dyke - Sunol CA, US

International Classification:

G06F 12/00

US Classification:

711154

Abstract:

A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.

US Patent:

8375368, Feb 12, 2013

Filed:

Mar 9, 2007

Appl. No.:

11/716508

Inventors:

Nathan D. Tuck - Corvallis OR, US
Matthew N. Papakipos - Palo Alto CA, US
Brian K. Grant - Cupertino CA, US
Christopher G. Demetriou - Redwood City CA, US
Jan Civlin - Sunnyvale CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 9/44

US Classification:

717130, 717131

Abstract:

A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of the parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. A profiling tool is used to collect, analyze, and visualize the performance data of an application in connection with its execution on a parallel-processing computer system through the runtime system. This profiling tool greatly enhances an application developer's ability to understand how an application is executed on the parallel-processing computer system and fine-tune the application to achieve high performance.