Naveen K Kini

age ~53

from San Jose, CA

Get Report
Also known as:
  • Naveen N Kini
  • Kuntadi N Kini
  • Kuntadi Naveen Kini
  • Kuntadi Nitin Kini
  • Knaveen N Kini
  • Nitin Kini
  • Naveen Kini Kuntadi
  • Nitin Kini Kuntadi
  • Kini Kuntadi
  • Amanda Marrero
Phone and address:
335 Elan Village Ln, San Jose, CA 95134
4085770576
Related to:
Connected to:

Naveen Kini Phones & Addresses

  • 335 Elan Village Ln, San Jose, CA 95134 • 4085770576
  • Austin, TX
  • Ocala, FL
  • Fremont, CA
  • Sunnyvale, CA
  • 1071 Foxhurst Way, San Jose, CA 95120

Work

  • Company:
    Western digital
    May 2016
  • Position:
    Director, ssd engineering

Education

  • Degree:
    Masters
  • School / High School:
    Binghamton University
    1994 to 1996
  • Specialities:
    Industrial Engineering

Skills

Manufacturing • Semiconductors • Product Development • Product Management • Design of Experiments • Continuous Improvement • Six Sigma • Failure Analysis • Process Engineering • Lean Manufacturing • Reliability • Engineering Management • Fmea • Supply Management • Quality System • Statistical Process Control • Product Lifecycle Management • Risk Management • Research and Development • Materials Science • Characterization • Supplier Quality • Statistical Data Analysis • Cost Reduction • Iso • Team Leadership • Multitasking • Teamwork • Cross Functional Team Leadership • Technology Development • Semiconductor Packaging • Smt • Component Engineering • Customer Quality

Languages

English • Hindi

Industries

Semiconductors

Us Patents

  • Pcb Circuit Modification From Multiple To Individual Chip Enable Signals

    view source
  • US Patent:
    7778057, Aug 17, 2010
  • Filed:
    Feb 26, 2007
  • Appl. No.:
    11/679157
  • Inventors:
    Michael McCarthy - San Jose CA, US
    Ning Ye - San Jose CA, US
    Naveen Kini - Fremont CA, US
  • Assignee:
    SanDisk Corporation - Milpitas CA
  • International Classification:
    G11C 5/02
  • US Classification:
    365 51, 365 63, 36518511, 365201, 36523003
  • Abstract:
    A semiconductor package is discussed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.

  • Electronic Component Including Micro Balls

    view source
  • US Patent:
    8637779, Jan 28, 2014
  • Filed:
    Jun 1, 2011
  • Appl. No.:
    13/151145
  • Inventors:
    Suresh Upadhyayula - San Jose CA, US
    Naveen Kini - San Jose CA, US
  • Assignee:
    SanDisk Technologies Inc. - Plano TX
  • International Classification:
    H01L 23/488
    H05K 1/11
  • US Classification:
    174261, 257738, 257E23023
  • Abstract:
    A system of micro balls is disclosed for coupling an electronic component to a printed circuit board. The micro balls have a small diameter, and each contact pad may include an array of two or more micro balls. An example of a micro ball may include a polymer core, surrounded by a copper layer, which is in turn surrounded by a layer of solder.

  • Method Of Making Pcb Circuit Modification From Multiple To Individual Chip Enable Signals

    view source
  • US Patent:
    20080206904, Aug 28, 2008
  • Filed:
    Feb 26, 2007
  • Appl. No.:
    11/679153
  • Inventors:
    Michael McCarthy - San Jose CA, US
    Ning Ye - San Jose CA, US
    Naveen Kini - Fremont CA, US
  • International Classification:
    H01L 21/66
  • US Classification:
    438 15, 257E21521
  • Abstract:
    A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.

  • Pcb Circuit Modification From Multiple To Individual Chip Enable Signals

    view source
  • US Patent:
    20100309707, Dec 9, 2010
  • Filed:
    Aug 16, 2010
  • Appl. No.:
    12/857365
  • Inventors:
    Michael McCarthy - San Jose CA, US
    Ning Ye - San Jose CA, US
    Naveen Kini - Fremont CA, US
  • International Classification:
    G11C 5/02
    G11C 29/00
  • US Classification:
    365 51, 365201
  • Abstract:
    A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.

  • Vias For Mitigating Pad Delamination

    view source
  • US Patent:
    20120281377, Nov 8, 2012
  • Filed:
    May 6, 2011
  • Appl. No.:
    13/102398
  • Inventors:
    Naveen Kini - San Jose CA, US
  • International Classification:
    H05K 1/18
  • US Classification:
    361767, 174262
  • Abstract:
    A signal carrier medium is disclosed including support vias for maintaining laminated portions of the signal carrier medium together. The signal carrier medium includes metal portions such as a contact pad. The metal portions may have one or more adjacent support vias for dissipating stresses which build in the metal portions.

  • Semiconductor Package With Dual Second Level Electrical Interconnections

    view source
  • US Patent:
    20160120031, Apr 28, 2016
  • Filed:
    Oct 22, 2014
  • Appl. No.:
    14/521303
  • Inventors:
    - Plano TX, US
    Naveen Kini - San Jose CA, US
    Elad Baram - Sunnyvale CA, US
    Pradip Ghimire - San Jose CA, US
  • Assignee:
    SanDisk Technologies Inc. - Plano TX
  • International Classification:
    H05K 1/11
    H05K 1/18
  • Abstract:
    A semiconductor package such as a multi-chip package is disclosed. The semiconductor package may be configured for dual second level interconnection onto a printed circuit board of a host device. Thus, a single semiconductor package may be used on host printed circuit boards having different configurations.

Resumes

Naveen Kini Photo 1

Director, Ssd Engineering

view source
Location:
1071 Foxhurst Way, San Jose, CA 95120
Industry:
Semiconductors
Work:
Western Digital
Director, Ssd Engineering
Sandisk Sep 1, 2003 - May 2016
Director - Packaging and Assembly Engineering
Solectron Jan 1999 - Sep 2003
Product Engineering Manager
Smart Modular Technologies Dec 1996 - Dec 1999
Senior Manufacturing Engineer
Universal Instruments Aug 1994 - Sep 1996
Research Associate - Bga and Dca Consortium
Education:
Binghamton University 1994 - 1996
Masters, Industrial Engineering Birla Institute of Technology and Science, Pilani 1989 - 1994
Bachelors, Mechanical Engineering Birla Institute of Technology and Science, Pilani 1989 - 1994
Masters, Mathematics Uc Berkeley College of Engineering
Skills:
Manufacturing
Semiconductors
Product Development
Product Management
Design of Experiments
Continuous Improvement
Six Sigma
Failure Analysis
Process Engineering
Lean Manufacturing
Reliability
Engineering Management
Fmea
Supply Management
Quality System
Statistical Process Control
Product Lifecycle Management
Risk Management
Research and Development
Materials Science
Characterization
Supplier Quality
Statistical Data Analysis
Cost Reduction
Iso
Team Leadership
Multitasking
Teamwork
Cross Functional Team Leadership
Technology Development
Semiconductor Packaging
Smt
Component Engineering
Customer Quality
Languages:
English
Hindi

Facebook

Naveen Kini Photo 2

Naveen Kini

view source
Naveen Kini Photo 3

Naveen Kini

view source

Youtube

8 GOLDEN RULES to make your child eat better

8 GOLDEN RULES to make your child eat better

Here are some simple rules to follow at home to overcome all the probl...

  • Duration:
    4m 9s

Project StepOne #DoctorDiaries - Dr Naveen Kini

Project StepOne #DoctorDiaries - Dr Naveen Kini

The #DoctorVolunteer... from #ProjectStepOne, share their experience ...

  • Duration:
    2m 14s

Discussion with Dr Naveen Kini

Discussion with Dr Naveen Kini

We had a wonderful opportunity to have a detailed discussion with Dr.N...

  • Duration:
    17m 48s

Wearing a mask - the why and the how

Wearing a mask - the why and the how

A paediatrician, Dr Naveen Kini's, attempt to help people understand t...

  • Duration:
    5m 14s

Cardio-Pulmonary Resuscitation: The basics of...

Cardio-Pulmonary Resuscitation: The basics of CPR

Here is a video detailing the basics of CPR, and how to go about it. T...

  • Duration:
    18m 29s

Choking: First aid and prevention

Choking: First aid and prevention

Here is a video on the causes, first aid and prevention of Choking in ...

  • Duration:
    13m 48s

Googleplus

Naveen Kini Photo 4

Naveen Kini

Naveen Kini Photo 5

Naveen Kini

Get Report for Naveen K Kini from San Jose, CA, age ~53
Control profile