Ngaiman C Chau

US Patent:

20070139446, Jun 21, 2007

Filed:

Dec 15, 2005

Appl. No.:

11/275149

Inventors:

Ngaiman CHAU - Arcadia CA, US
Chia-Hao LEE - Hacienda Heights CA, US
John Wu - Rancho Palos Verdes CA, US

Assignee:

XEROX CORPORATION - Stamford CT

International Classification:

G09G 5/00

US Classification:

345660000

Abstract:

A system and method are provided by which a user, at a client workstation, can efficiently, simply and effectively manipulate, and specifically crop, a high resolution image that has been scanned and/or otherwise stored in a server with which the client worksation is in web-based communication. The disclosed system and method reduce and/or eliminate the need to transfer a file containing a full high resolution image from the server to the client workstation across a web-based data transfer network. A cropping request may be generated by a user via a client workstation and only that request may be transferred to, and implemented through, the server, eliminating significant data transfer requirements regarding the transfer of the extremely large files associated with high resolution images required of conventional cropping methods. An addition advantage is reduction and/or elimination of a need for sophisticated image display and processing software to reside within each client workstation.

US Patent:

46581588, Apr 14, 1987

Filed:

Jul 3, 1980

Appl. No.:

6/165518

Inventors:

Ngaiman Chau - Flintridge CA
John W. Wu - Torrance CA
Neng-Tze Yang - Rancho Palos Verdes CA
Eugene J. Mar - Sunnyvale CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H03K 524
G11C 706
G11C 1140

US Classification:

307530

Abstract:

In a high-density VLSI NMOS semiconductor such as a ROM, a voltage sensing mode amplifier in the output thereof, operative to sense relatively very low input signal swing bit read signals from the ROM with relative insensitivity to fabrication process variation. The structure includes a common gate amplifier for receiving the ROM signal, a very sensitive reference voltage circuit, a two-stage differential digital switching module operative to compatively receive the common gate and voltage reference signals to effectively distinguish relatively weak bit signals as read from the high-density VLSI ROM.