Nhan H Do

US Patent:

20220391682, Dec 8, 2022

Filed:

Aug 10, 2022

Appl. No.:

17/885431

Inventors:

- San Jose CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US

International Classification:

G06N 3/063
G06N 3/04
G06F 3/06
G06F 17/16
G06N 3/08
G11C 11/56
G11C 13/00
G11C 16/04
G11C 16/28

Abstract:

Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving a first voltage, multiplying the first voltage by a coefficient to generate a second voltage, applying the first voltage to a gate of one of a reference transistor and a selected memory cell, applying the second voltage to a gate of the other of a reference transistor and a selected memory cell, and using the reference transistor in a sense operation to determine a value stored in the selected memory cell.

US Patent:

20220383087, Dec 1, 2022

Filed:

Aug 10, 2022

Appl. No.:

17/885437

Inventors:

- San Jose CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US

International Classification:

G06N 3/063
G06N 3/04
G06F 3/06
G06F 17/16
G06N 3/08
G11C 11/56
G11C 13/00
G11C 16/04
G11C 16/28

Abstract:

Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

US Patent:

20220320125, Oct 6, 2022

Filed:

Jun 21, 2022

Appl. No.:

17/845782

Inventors:

- San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Nhan Do - Saratoga CA, US

International Classification:

H01L 27/11526
H01L 27/11519
H01L 27/11521
G11C 16/04
G11C 16/14
G11C 16/26
H01L 29/423
H01L 29/788

Abstract:

A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

US Patent:

20220231037, Jul 21, 2022

Filed:

Apr 8, 2022

Appl. No.:

17/716950

Inventors:

- San Jose CA, US
CATHERINE DECOBERT - Pourrieres, FR
FENG ZHOU - Fremont CA, US
JINHO KIM - Saratoga CA, US
XIAN LIU - Sunnyvale CA, US
NHAN DO - Saratoga CA, US

International Classification:

H01L 27/11517
H01L 29/423
H01L 29/66
H01L 29/78
H01L 29/788

Abstract:

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

US Patent:

20210142854, May 13, 2021

Filed:

Dec 17, 2020

Appl. No.:

17/125459

Inventors:

- San Jose CA, US
Vipin Tiwari - Dublin CA, US
Nhan Do - Saratoga CA, US
Mark Reiten - Alamo CA, US

International Classification:

G11C 16/10
G11C 16/16
G06N 3/063

Abstract:

Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.

US Patent:

20200233482, Jul 23, 2020

Filed:

Mar 14, 2019

Appl. No.:

16/354040

Inventors:

- San Jose CA, US
Vipin Tiwari - Dublin CA, US
Mark Reiten - Alamo CA, US
Nhan Do - Saratoga CA, US

International Classification:

G06F 1/3234
G11C 16/04
G11C 11/54
G06F 17/16
G06N 3/08

Abstract:

Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

US Patent:

20200234111, Jul 23, 2020

Filed:

Mar 14, 2019

Appl. No.:

16/353830

Inventors:

- San Jose CA, US
Vipin Tiwari - Dublin CA, US
Mark Reiten - Alamo CA, US
Nhan Do - Saratoga CA, US

International Classification:

G06N 3/08
G06N 3/04
G11C 16/04

Abstract:

Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network. Numerous embodiments are disclosed for converting the neuron current-based time pulses into analog current or voltage values if an analog input is needed for the VMM array.

US Patent:

20200176578, Jun 4, 2020

Filed:

Dec 3, 2018

Appl. No.:

16/208288

Inventors:

- San Jose CA, US
Catherine Decobert - Pourrieres, FR
Feng Zhou - Fremont CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Nhan Do - Saratoga CA, US

International Classification:

H01L 29/423
H01L 29/78
H01L 29/08
H01L 29/10
H01L 27/11521
H01L 29/66
G11C 16/04
G11C 16/10
G11C 16/14
G11C 16/26
H01L 29/788

Abstract:

A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.