Nhan Hoi Do

US Patent:

20020140010, Oct 3, 2002

Filed:

Mar 29, 2001

Appl. No.:

09/821320

Inventors:

Truc Vu - Tustin CA, US
Frank Calabretta - Costa Mesa CA, US
James Asbrock - Oceanside CA, US
Nhan Do - San Jose CA, US

International Classification:

H04N005/335

US Classification:

257/294000, 348/294000

Abstract:

A detector with a transistor sensitive to electromagnetic energy. In accordance with the present teachings, the transistor is biased such that the output thereof is responsive to the electromagnetic energy. The inventive imager includes an array of the novel detectors. Each of the detectors being an n-channel metal-oxide semiconductor transistor with a floating body. The transistors are biased for selective activation and sequential readout. The transistor outputs are read by a differential current sense amplifier. A color filter is disclosed to provide a color sense capability. As an alternative, a grating is provided for this purpose. The present invention allows a very dense imager to be built on using conventional silicon on sapphire or silicon on insulator complementary metal-oxide semiconductor processes. The use of standard CMOS processes allows for low manufacturing costs.

US Patent:

61408328, Oct 31, 2000

Filed:

Jun 5, 1998

Appl. No.:

9/092387

Inventors:

Truc Q. Vu - Tustin CA
Emad S. Zawaideh - Encinitas CA
Nhan T. Do - Irvine CA
Glenn M. Kramer - Vista CA

Assignee:

Raytheon Company - Lexington MA

International Classification:

G01R 3126
G01R 3102
G01R 104
G06F 1100

US Classification:

324765

Abstract:

A method that uses effective widths of NMOS and PMOS devices in a digital circuit and their intrinsic junction and subthreshold leakage currents to produce a specification for IDDQ, the range of IDDQ, and the delta of IDDQ between pre- and post-overvoltage stress tests to screen out defective integrated circuits having excessive extrinsic current leakage. The present invention provides for a computer-implemented method that generates an indication of whether IDDQ values associated with integrated circuits that have been tested are within the IDDQ specification or not. This processing eliminates the need for time-intensive and costly burn-in testing on the integrated circuits.