Nicholas P Carter

US Patent:

7928989, Apr 19, 2011

Filed:

Dec 12, 2006

Appl. No.:

11/609763

Inventors:

Patrick R. Brown - Raleigh NC, US
Eric S. Werness - San Jose CA, US
Barthold B. Lichtenbelt - Fort Collins CO, US
Nicholas B. Carter - Seattle WA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/02
G06F 15/00
G06T 1/00
G06T 1/20

US Classification:

345543, 345501, 345506

Abstract:

One embodiment of the invention is a method for storing transformed vertex attributes that includes the steps of allocating memory space for a transform feedback buffer, selecting one or more transformed vertex attributes to store in the transform feedback buffer independently of any shader programs executing on any processing units in the graphics rendering pipeline, configuring the transform feedback buffer to store the one or more transformed vertex attributes, and initiating a processing mode wherein vertex data is processed in the graphics rendering pipeline to produce the transformed vertices, the attributes of which are then written to the transform feedback buffer. One advantage is that the transform feedback buffer can be used to store and access transformed vertices, without having to convert the vertex data to a pixel format, store the pixels in a frame buffer, and then convert the pixels back to a vertex format.

US Patent:

58453318, Dec 1, 1998

Filed:

Sep 28, 1994

Appl. No.:

8/314013

Inventors:

Nicholas P. Carter - Somerville MA
Stephen W. Keckler - Cambridge MA
William J. Dally - Framingham MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 1210

US Classification:

711163

Abstract:

A multiprocessor system having shared memory uses guarded pointers to identify protected segments of memory and permitted access to a location specified by the guarded pointer. Modification of pointers is restricted by the hardware system to limit access to memory segments and to limit operations which can be performed within the memory segments. Global address translation is based on grouping of pages which may be stored across multiple nodes. The page groups are identified in the global translation of each node and, with the virtual address, identify a node in which data is stored. Pages are subdivided into blocks and block status flags are stored for each page. The block status flags indicate whether a memory location may be read or written into at a particular node and indicate to a home node whether a remote node has written new data into a location.

US Patent:

60031239, Dec 14, 1999

Filed:

Feb 10, 1998

Appl. No.:

9/021658

Inventors:

Nicholas P. Carter - Somerville MA
Stephen W. Keckler - Cambridge MA
William J. Dally - Framingham MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 1210

US Classification:

711207

Abstract:

A multiprocessor system having shared memory uses guarded pointers to identify protected segments of memory and permitted access to a location specified by the guarded pointer. Modification of pointers is restricted by the hardware system to limit access to memory segments and to limit operations which can be performed within the memory segments. Global address translation is based on grouping of pages which may be stored across multiple nodes. The page groups are identified in the global translation of each node and, with the virtual address, identify a node in which data is stored. Pages are subdivided into blocks and block status flags are stored for each page. The block status flags indicate whether a memory location may be read or written into at a particular node and indicate to a home node whether a remote node has written new data into a location.

US Patent:

20180165381, Jun 14, 2018

Filed:

Dec 12, 2016

Appl. No.:

15/376172

Inventors:

- Santa Clara CA, US
Nicholas P. Carter - SOMERVILLE MA, US
Deborah T. Marr - Portland OR, US

International Classification:

G06F 17/30

Abstract:

A processor may include a gather-update-scatter accelerator, and circuitry to direct an instruction to the accelerator for execution. The instruction may include a search index, an operation to be performed, and a scalar data value. The accelerator may include a content-associative memory (CAM) storing multiple entries, each of which stores a respective index key and a data value associated with the index key. The accelerator may include a CAM controller, including circuitry to select, based on the information in the instruction, one of the plurality of entries in the CAM on which to operate, an arithmetic logic unit (ALU), including circuitry to perform an arithmetic or logical operation on the selected entry, the operation being dependent on the information in the instruction, and circuitry to store a result of the operation in the selected entry in the CAM.