Nicholas Todd Humphries

US Patent:

7872937, Jan 18, 2011

Filed:

Mar 31, 2008

Appl. No.:

12/059641

Inventors:

Shawn Searles - Austin TX, US
Faisal A. Syed - Austin TX, US
Nicholas T. Humphries - Austin TX, US

International Classification:

G11C 8/00

US Classification:

36523006, 365191, 365193, 36523008, 3652331

Abstract:

A data driver includes a first latch (), an extension logic circuit (), and a second latch (). The first latch () has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit () has an input coupled to the output of the first latch (), a control input for receiving a control signal, and an output. The extension logic circuit () selectively delays the output of the first latch () in response to the control signal. The second latch () has an input coupled to the output of the extension logic circuit (), a clock input for receiving a second clock signal, and an output for providing an output data signal.

US Patent:

7929361, Apr 19, 2011

Filed:

Mar 31, 2008

Appl. No.:

12/059613

Inventors:

Shawn Searles - Austin TX, US
Faisal A. Syed - Austin TX, US
Nicholas T. Humphries - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 7/00

US Classification:

365194, 365193, 3652331, 36523319, 713400, 713401

Abstract:

A transceiver () includes a receive circuit (), a transmit circuit (), a shared delay locked loop (DLL) (), and a controller (). The receive circuit () has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit () has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller () enables the shared DLL () for use by the receive circuit () during a receive cycle, and enables the shared DLL () for use by the transmit circuit () during a transmit cycle.

US Patent:

8356155, Jan 15, 2013

Filed:

Oct 22, 2010

Appl. No.:

12/910412

Inventors:

Shawn Searles - Austin TX, US
Nicholas T. Humphries - Austin TX, US
Brian W. Amick - Bedford MA, US
Richard W. Reeves - Westborough MA, US
Hanwoo Cho - Acton MA, US
Ronald L. Pettyjohn - Concord MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711167, 711E12001

Abstract:

A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

US Patent:

20090244995, Oct 1, 2009

Filed:

Mar 31, 2008

Appl. No.:

12/059593

Inventors:

Shawn Searles - Austin TX, US
Faisal A. Syed - Austin TX, US
Nicholas T. Humphries - Austin TX, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G11C 7/22

US Classification:

365194, 327161, 327158

Abstract:

A receive circuit () includes a DLL core (), a latch (), and a DLL control circuit (). The DLL core () has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch () has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (), and an output for providing an internal data signal. The DLL control circuit () provides the DLL clock signal to the first input of the DLL core () responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core () responsive to a processor clock signal while the receive circuit () is in a second mode.

US Patent:

20130124806, May 16, 2013

Filed:

Jan 9, 2013

Appl. No.:

13/737306

Inventors:

Nicholas Todd HUMPHRIES - Austin TX, US
Brian W. AMICK - Bedford MA, US
Richard W. REEVES - Westborough MA, US
Hanwoo CHO - Acton MA, US
Ronald L. PETTYJOHN - Concord MA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711154

Abstract:

A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

US Patent:

20200225954, Jul 16, 2020

Filed:

Mar 6, 2019

Appl. No.:

16/294916

Inventors:

- Suwon-si, KR
Nicholas HUMPHRIES - Austin TX, US
Ken Yu LIM - Cedar Park TX, US
Ryan HENSLEY - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/0875

Abstract:

A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.

US Patent:

20180210706, Jul 26, 2018

Filed:

Mar 23, 2018

Appl. No.:

15/934911

Inventors:

- Suwon-si, KR
Nicholas Todd HUMPHRIES - Austin TX, US
Marc AUGUSTIN - Austin TX, US

International Classification:

G06F 7/483
G06F 7/499
G06F 9/48

Abstract:

Embodiments of the present disclosure include a tininess prediction and handler engine for handling numeric underflow while streamlining the data path for handling normal range cases, thereby avoiding flushes, and reducing the complexity of a scheduler with respect to how dependent operations are handled. A preemptive tiny detection logic section can detect a potential tiny result for the function or operation that is being performed, and can produce a pessimistic tiny indicator. The tininess prediction and handler engine can further include a subnormal post-processing pipe, which can denormalize and round one or more subnormal operations while in a post-processing mode. A schedule modification logic section can reschedule in-flight operations. The schedule modification logic section can issue dependent operations optimistically assuming that a producing operation will not produce a tiny result, and so will not incur extra latency associated with fixing the tiny result in the post-processing pipe.

US Patent:

20170060533, Mar 2, 2017

Filed:

Mar 10, 2016

Appl. No.:

15/067159

Inventors:

- Suwon-si, KR
Nicholas Todd HUMPHRIES - Austin TX, US
Marc AUGUSTIN - Austin TX, US

International Classification:

G06F 7/483
G06F 9/48
G06F 7/499

Abstract:

Embodiments of the present disclosure include a tininess prediction and handler engine for handling numeric underflow while streamlining the data path for handling normal range cases, thereby avoiding flushes, and reducing the complexity of a scheduler with respect to how dependent operations are handled. A preemptive tiny detection logic section can detect a potential tiny result for the function or operation that is being performed, and can produce a pessimistic tiny indicator. The tininess prediction and handler engine can further include a subnormal post-processing pipe, which can denormalize and round one or more subnormal operations while in a post-processing mode. A schedule modification logic section can reschedule in-flight operations. The schedule modification logic section can issue dependent operations optimistically assuming that a producing operation will not produce a tiny result, and so will not incur extra latency associated with fixing the tiny result in the post-processing pipe.