Nicholas C Neal

US Patent:

20210257277, Aug 19, 2021

Filed:

Feb 19, 2020

Appl. No.:

16/794789

Inventors:

- Santa Clara CA, US
Kyle ARRINGTON - Gilbert AZ, US
Shankar DEVASENATHIPATHY - Tempe AZ, US
Aaron MCCANN - Queen Creek AZ, US
Nicholas NEAL - Gilbert AZ, US
Zhimin WAN - Chandler AZ, US

International Classification:

H01L 23/433
H01L 23/367
H01L 25/065

Abstract:

Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

US Patent:

20210249330, Aug 12, 2021

Filed:

Feb 6, 2020

Appl. No.:

16/783804

Inventors:

- Santa Clara CA, US
Nicholas Neal - Gilbert AZ, US

International Classification:

H01L 23/367
H01L 23/473
H01L 21/50

Abstract:

Embodiments herein relate to systems, techniques, and/or processes directed to a composite thermal matrix structure to provide thermal conductivity within a package. The composite thermal matrix may include a first material that is substantially solid and a second material that is liquid and absorbed into the first material. A package may include the composite thermal matrix within an integrated heat sink coupled with a printed circuit board and encapsulating one or more die where the thermal matrix structure is in a state of compressive stress within the heat sink. The thermal matrix structure may expand and contract as the heat sink warps during thermal cycling to maintain constant thermal conductivity with low stress on the package.

US Patent:

20210242107, Aug 5, 2021

Filed:

Feb 4, 2020

Appl. No.:

16/781563

Inventors:

- Santa Clara CA, US
Edvin CETEGEN - Chandler AZ, US
Nicholas S. HAEHN - Scottsdale AZ, US
Mitul MODI - Phoenix AZ, US
Nicholas NEAL - Gilbert AZ, US

International Classification:

H01L 23/373
H01L 23/00
H01L 23/367

Abstract:

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

US Patent:

20210104490, Apr 8, 2021

Filed:

Oct 8, 2019

Appl. No.:

16/596367

Inventors:

- Santa Clara CA, US
Edvin CETEGEN - Chandler AZ, US
Nicholas S. HAEHN - Scottsdale AZ, US
Ram S. VISWANATH - Phoenix AZ, US
Nicholas NEAL - Gilbert AZ, US
Mitul MODI - Phoenix AZ, US

International Classification:

H01L 25/065
H01L 23/31
H01L 23/498
H01L 23/00
H01L 21/56
H01L 21/78
H01L 21/48

Abstract:

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

US Patent:

20210066162, Mar 4, 2021

Filed:

Aug 30, 2019

Appl. No.:

16/557896

Inventors:

- Santa Clara CA, US
Nicholas S. HAEHN - Scottsdale AZ, US
Edvin CETEGEN - Chandler AZ, US
Nicholas NEAL - Scottsdale AZ, US
Jacob VEHONSKY - Gilbert AZ, US
Steve S. CHO - Chandler AZ, US
Rahul JAIN - Gilbert AZ, US
Antariksh Rao Pratap SINGH - Gilbert AZ, US
Tarek A. IBRAHIM - Mesa AZ, US
Thomas HEATON - Mesa AZ, US
Vipul MEHTA - Chandler AZ, US

International Classification:

H01L 23/42
H01L 23/00

Abstract:

A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.

US Patent:

20210020531, Jan 21, 2021

Filed:

Jul 15, 2019

Appl. No.:

16/511360

Inventors:

- Santa Clara CA, US
Jacob VEHONSKY - Gilbert AZ, US
Nicholas S. HAEHN - Scottsdale AZ, US
Thomas HEATON - Mesa AZ, US
Steve S. CHO - Chandler AZ, US
Rahul JAIN - Gilbert AZ, US
Tarek IBRAHIM - Mesa AZ, US
Antariksh Rao Pratap SINGH - Gilbert AZ, US
Nicholas NEAL - Scottsdale AZ, US
Sergio CHAN ARGUEDAS - Chandler AZ, US
Vipul MEHTA - Chandler AZ, US

International Classification:

H01L 23/16
H01L 23/31
H01L 23/498
H01L 23/00
H01L 25/065

Abstract:

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

US Patent:

20210020532, Jan 21, 2021

Filed:

Jul 15, 2019

Appl. No.:

16/511376

Inventors:

- Santa Clara CA, US
Nicholas S. HAEHN - Scottsdale AZ, US
Thomas HEATON - Mesa AZ, US
Steve S. CHO - Chandler AZ, US
Rahul JAIN - Gilbert AZ, US
Tarek IBRAHIM - Mesa AZ, US
Antariksh Rao Pratap SINGH - Gilbert AZ, US
Edvin CETEGEN - Chandler AZ, US
Nicholas NEAL - Scottsdale AZ, US
Sergio CHAN ARGUEDAS - Gilbert AZ, US

International Classification:

H01L 23/16
H01L 23/498
H01L 23/00
H01L 23/367

Abstract:

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

US Patent:

20200194330, Jun 18, 2020

Filed:

Dec 13, 2018

Appl. No.:

16/219158

Inventors:

- Santa Clara CA, US
Nicholas Neal - Gilbert AZ, US
Chandra Mohan Jha - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/367
H01L 23/498
H01L 23/522
H01L 23/538
H01L 23/373
H01L 23/00

Abstract:

Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.