Nicholas B Peterson

US Patent:

55354203, Jul 9, 1996

Filed:

Dec 14, 1994

Appl. No.:

8/356131

Inventors:

James Kardach - San Jose CA
Sung S. Cho - Sunnyvale CA
Nicholas B. Peterson - San Jose CA
Thomas R. Lane - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1324

US Classification:

395868

Abstract:

A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.

US Patent:

60553723, Apr 25, 2000

Filed:

May 1, 1997

Appl. No.:

8/845634

Inventors:

James Kardach - San Jose CA
Sung Soo Cho - Sunnyvale CA
Nicholas B. Peterson - San Jose CA
Thomas R Lane - San Jose CA
Jayesh M. Joshi - Santa Clara CA
Neil Songer - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 946

US Classification:

395734

Abstract:

A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

US Patent:

56714211, Sep 23, 1997

Filed:

Dec 7, 1994

Appl. No.:

8/351637

Inventors:

James Kardach - San Jose CA
Sung Soo Cho - Sunnyvale CA
Nicholas B. Peterson - San Jose CA
Thomas R. Lane - San Jose CA
Jayesh M. Joshi - Santa Clara CA
Neil Songer - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 946
G06F 1314

US Classification:

395733

Abstract:

A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

US Patent:

20150188548, Jul 2, 2015

Filed:

Oct 13, 2014

Appl. No.:

14/513024

Inventors:

- Santa Clara CA, US
Huang K. Boddu - Pleasanton CA, US
Stefan Rusu - Santa Clara CA, US
Nicholas B. Peterson - San Jose CA, US

International Classification:

H03L 7/07

Abstract:

Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.

US Patent:

20140266340, Sep 18, 2014

Filed:

Jun 27, 2013

Appl. No.:

13/929164

Inventors:

CHOUPIN HUANG - San Jose CA, US
VIJAYA K. BODDU - Pleasanton CA, US
STEFAN RUSU - Santa Clara CA, US
NICHOLAS B. PETERSON - San Jose CA, US

International Classification:

H03L 7/07

US Classification:

327156

Abstract:

Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.