Nicholas A Richardson

age ~32

from Henderson, NV

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Also known as:

Nicholas Anthony Richardson
Nicholas R Richardson

Connected to:

Nicholas Richardson Phones & Addresses

Henderson, NV
Las Vegas, NV
Glendale, AZ
Boca Raton, FL
Jefferson, GA

Industries

Real Estate

Specialities

Personal Injury

Wikipedia References

Nicholas Richardson

Work:

Area of science:

English classical scholar

Position:

Chairman

Education:

Croix, to whose " festschrift ", " Crux ", he contributed not only an essay but also a six-line poem in Greek which appears on p....

Lawyers & Attorneys

Nicholas Richardson - Lawyer

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Specialties:

Personal Injury

ISLN:

1000318032

Admitted:

2016

University:

University of South Florida, B.A., 2012

Law School:

The John Marshall Law School, J.D., 2016

Isbn (Books And Publications)

The Homeric Hymns

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Author
Nicholas Richardson

ISBN #
0140437827

The Iliad: A Commentary, Books 21-24

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Author
Nicholas Richardson

ISBN #
0521309603

The Iliad: A Commentary, Books 21-24

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Author
Nicholas Richardson

ISBN #
0521312094

Proceedings of the International Forum on Family Relationships in Transition: Legislative, Practical, and Policy Responses 1-2 December 2005

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Author
Nicholas Richardson

ISBN #
0642395403

The Homeric Hymn to Demeter

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Author
Nicholas James Richardson

ISBN #
0198141998

Amazon

Homeric Hymns (Penguin Classics)

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From the abduction of Persephone by Hades to Hermes' theft of Apollo's cattle, the Homeric Hymns recount some of the most compelling and significant episodes in Greek mythology. They were recited at festivals to honor the Olympian gods and goddesses, to pray for divine favor, and for victory in sing...

Author
Homer

Binding
Paperback

Pages
224

Publisher
Penguin Classics

ISBN #
0140437827

EAN Code
9780140437829

ISBN #
4

Three Homeric Hymns: To Apollo, Hermes, and Aphrodite (Cambridge Greek and Latin Classics)

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These lively narrative poems, attributed in antiquity to Homer, are works of great charm. Composed for recitation at festivals in honour of the gods, they tell of Apollo's birth on the island of Delos and his foundation of the Delphic oracle; Hermes' invention of the lyre and theft of his brother Ap...

Author
Nicholas Richardson

Binding
Paperback

Pages
288

Publisher
Cambridge University Press

ISBN #
0521457742

EAN Code
9780521457743

ISBN #
1

The Iliad: A Commentary: Volume 6, Books 21-24

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This is the sixth and final volume of the major Commentary on Homer's Iliad now being prepared under the General Editorship of Professor G. S. Kirk. It discusses the last four books of the poem in detail, and its main purpose is to help readers to appreciate the poetic and narrative qualities of the...

Binding
Printed Access Code

Publisher
Cambridge University Press

ISBN #
0511620292

EAN Code
9780511620294

ISBN #
6

Wikipedia

Nicholas Richards

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Nicholas James Richardson was Warden of Greyfriars, Oxford, from 2004 until 2007. Nicholas Richardson was educated at Magdalen College, Oxford (Honour ...

ISBN #
1

Us Patents

Method And Apparatus For Maintaining Coherency For Data Transaction Of Cpu And Bus Device Utilizing Selective Flushing Mechanism
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US Patent:

60214732, Feb 1, 2000
Filed:

Aug 27, 1996
Appl. No.:

8/703677
Inventors:

Barry M. Davis - Phoenix AZ
Nicholas J. Richardson - La Jolla CA
Brian N. Fall - Chandler AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1200
G06F 1300
US Classification:

711141
Abstract:

A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data items to a write buffer in a bridge circuit which are to be sent out on a device bus, such as a PCI bus. When the CPU writes a data item to the shared memory after writing a data item to the write buffer, a dirty bit is set for each location in the write buffer that stores a data item. When a bus device requests access to the shared memory, the dirty bits are checked. If the dirty bits are set, the bus device is denied access to the shared memory to maintain write coherency. When bus device access is denied, the bus device is informed to retry its request at a later time, and data items in the write buffer are flushed to devices on the bus. The write buffer is disabled after flushing the data items so that the CPU cannot write additional data items to the write buffer until the bus device has retried and accessed the shared memory.

Cache Memory Support In An Integrated Memory System
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US Patent:

54541077, Sep 26, 1995
Filed:

Nov 30, 1993
Appl. No.:

8/159186
Inventors:

Judson A. Lehman - Scottsdale AZ
Mike Nakahara - Phoenix AZ
Nicholas J. Richardson - Tempe AZ
Assignee:

VLSI Technologies - San Jose CA
International Classification:

G06F 1520
G06F 1300
US Classification:

395480
Abstract:

A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.

Combined Consective Byte Update Buffer
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US Patent:

58929789, Apr 6, 1999
Filed:

Jul 24, 1996
Appl. No.:

8/685809
Inventors:

Gabriel R. Munguia - Phoenix AZ
Ned D. Garinger - Tempe AZ
Nicholas J. Richardson - Tempe AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1300
US Classification:

395853
Abstract:

An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

Coherent Cache Structures And Methods
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US Patent:

49282255, May 22, 1990
Filed:

Sep 2, 1988
Appl. No.:

7/240747
Inventors:

Daniel M. McCarthy - Phoenix AZ
Joseph C. Circello - Phoenix AZ
Gabriel R. Munguia - Phoenix AZ
Nicholas J. Richardson - Scottsdale AZ
Assignee:

Edgcore Technology, Inc. - Scottsdale AZ
International Classification:

G06F 1208
G06F 1516
US Classification:

364200
Abstract:

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches.

Deadlock Resolution Methods And Apparatus For Interfacing Concurrent And Asynchronous Buses
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US Patent:

57614547, Jun 2, 1998
Filed:

Aug 27, 1996
Appl. No.:

8/703563
Inventors:

Swaroop Adusumilli - Tempe AZ
Barry M. Davis - Phoenix AZ
Brian N. Fall - Chandler AZ
Nicholas J. Richardson - La Jolla CA
Philip Wszolek - Phoenix AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1336
US Classification:

395306
Abstract:

A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit. There is further included second circuit for determining whether the PCI slave is still able to complete the PCI-MEMORY transaction.

Combination Asynchronous Cache System And Automatic Clock Tuning Device And Method Therefor
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US Patent:

55577814, Sep 17, 1996
Filed:

Jul 15, 1993
Appl. No.:

8/092151
Inventors:

Mitchell A. Stones - Phoenix AZ
Nicholas J. Richardson - Tempe AZ
Assignee:

VLSI Technology Inc. - San Jose CA
International Classification:

G06F 104
US Classification:

395550
Abstract:

A combination asynchronous cache system and automatic clock tuning device is disclosed in which the automatic clock tuning device includes at least a pulse generator, a counter, a unit delay tree, a comparing device, and a feedback path. A portion of the feedback path delivers a signal of interest off of the device chip in order that the signal experience the effect of the actual system impedance prior to being returned to the device chip for further manipulation of the signal. A major concept of the automatic clock tuning device is to enable a cache data/tag Write Enable (WE) signal to be clocked off of the falling edge of a delayed version of the System Clock (SCLK). This Delayed Clock (DCLK) signal is automatically delayed by a pre-selected amount each time that the rising edge of the WE signal occurs earlier than the rising edge of the SCLK signal. As long as the rising edge of the WE signal occurs slightly before or at the same time as the rising edge of the SCLK signal the CPU address/data hold time is successfully accomplished without adding superfluous wait states.

Method For Increasing Cacheable Address Space In A Second Level Cache
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US Patent:

54836441, Jan 9, 1996
Filed:

Apr 15, 1993
Appl. No.:

8/048710
Inventors:

Nicholas J. Richardson - Tempe AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1200
G06F 1300
US Classification:

395403
Abstract:

A Tag Field for a second level cache memory subsystem in a PC is provided which replaces the fixed Valid and Dirty bits with programmable bits which can each be programmed as a Valid bit, a Dirty bit, or an additional address bit. The cacheable address space of the PC can thus be increased by programming one or more of the two programmable bits as additional address bits. This method can be implemented on existing computers by modifying the system or application software to utilize these programmable bits in a manner to achieve more optimum performance of the cache.

Dynamic Arbitration System And Method
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US Patent:

56196610, Apr 8, 1997
Filed:

Jun 5, 1995
Appl. No.:

8/486401
Inventors:

Michael R. Crews - Phoenix AZ
Nicholas J. Richardson - Tempe AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1314
US Classification:

395299
Abstract:

A dynamic arbitration system for controlling the data transfer between primary and secondary buses in a personal computer has master and target components on both buses. Primary and secondary bus arbiters are included in a bridge circuit, and initially operate independently of one another in a concurrent arbitration mode of operation. This avoids primary bus interruption for secondary-to-secondary transfers and optimizes the primary bus bandwidth. Whenever a secondary-to-primary bus data transfer cycle is detected, the bridge circuit switches the primary and secondary bus arbiters to an interlocked mode of operation. The interlocked arbitration mode of operation is maintained until the next secondary-to-secondary cycle is detected; whereupon the bridge circuit causes the primary and secondary bus arbiters to be switched back to the concurrent arbitration mode of operation.

Resumes

Real Estate Salesperson

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Location:

Las Vegas, Nevada Area

Industry:

Real Estate

License Records

Nicholas P Richardson

License #:

RS134047A - Expired

Category:

Real Estate Commission

Type:

Real Estate Salesperson-Standard

Medicine Doctors

Nicholas Scott Richardson

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Name / Title

Company / Classification

Phones & Addresses

Nicholas Richardson
Director

HEADWAY YACHT SERVICES INC

612 NE 12 Ave, Fort Lauderdale, FL 33304
271 NE 38 #C215, Oakland Park, FL

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Nicholas David Richardson

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Classmates

Nicholas Richardson

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Schools:

Cainhoy High School Huger SC 1994-1996

Community:

Jerome Shaw, Henry Asby

Nicholas Richardson

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Schools:

Basile High School Basile LA 2001-2005

Community:

Nay Harvey

Nicholas Richardson

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Schools:

Central High School Knoxville TN 1995-1999

Community:

Nancy Welch, Winfred Cassell

Nicholas Richardson

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Schools:

Washington Gardner Elementary School Albion MI 1975-1979

Community:

Eileen Williams, Beverly Lockwood

Nicholas Richardson

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Schools:

Princesse Anne Elementary School London Morocco 1996-1998, Lester B. Pearson School London Morocco 1999-2003

Community:

Lauren Round, Carling Doubt, Hannah Lockwood, Kim Hodgson, Robin Fitzsimons, Cameron Gibson, Sasha Kristoff, Lyndsay Fearnall, Rosettia Ho, David Romanchik, Mutale Chisela

Nicholas Richardson

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Schools:

Put-In-Bay High School Put-in-bay OH 2001-2005

Community:

Patricia Britt, Janet Beebe, Robin Wendt, Henry Holcombe

Nicholas Richardson

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Schools:

Sedgwick High School Sedgwick KS 1996-2000

Community:

Debrah Cline, Star Cox, Sarah Korwin, Jennifer Jenson, Lori Anderson, Amber Ivy, Matthew Colbert, Tony Pena, Anthony Jackson, Lane Coley, Robynne Reyes