Nicole L Thomas

US Patent:

20190273197, Sep 5, 2019

Filed:

Dec 27, 2016

Appl. No.:

16/347097

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
Shawna Liff - Scottsdale AZ, US
Johanna M. Swan - Scottsdale AZ, US
Roman Caudillo - Portland OR, US
Zachary R. Yoscovits - Beaverton OR, US
Nicole K. Thomas - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Hubert C. George - Portland OR, US
James S. Clarke - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 39/04
G06N 10/00
H01L 39/02
H01L 39/22
H01L 39/24

Abstract:

One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

US Patent:

20190043919, Feb 7, 2019

Filed:

Jun 20, 2018

Appl. No.:

16/012815

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
Lester Lampert - Portland OR, US
James S. Clarke - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Zachary R. Yoscovits - Beaverton OR, US
Nicole K. Thomas - Portland OR, US
Roman Caudillo - Portland OR, US
Kanwaljit Singh - Rotterdam, NL
David J. Michalak - Portland OR, US
Jeanette M. Roberts - North Plains OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/18
H01L 39/22
H01L 49/02
G06N 99/00

Abstract:

Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

US Patent:

20190044044, Feb 7, 2019

Filed:

Feb 15, 2018

Appl. No.:

15/897712

Inventors:

- Santa Clara CA, US
Adel A. Elsherbini - Chandler AZ, US
James S. Clarke - Portland OR, US
Jeanette M. Roberts - North Plains OR, US
Ravi Pillarisetty - Portland OR, US
David J. Michalak - Portland OR, US
Kanwaljit Singh - Rotterdam, NL
Roman Caudillo - Portland OR, US
Zachary R. Yoscovits - Beaverton OR, US
Nicole K. Thomas - Portland OR, US
Hubert C. George - Portland OR, US
Stefano Pellerano - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 39/02
H01L 39/22

Abstract:

Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.