Nikhil Gupta

US Patent:

20230018221, Jan 19, 2023

Filed:

Sep 26, 2022

Appl. No.:

17/953002

Inventors:

Reshma Pattan - Tuam, IE
Pinkesh Shah - Chandler AZ, US
Chris MacNamara - Limerick, IE
Nikhil Gupta - Portland OR, US

International Classification:

G06F 1/3293
G06F 1/3287

Abstract:

An apparatus can include processor cores and control circuitry coupled to the processor cores. The control circuitry can detect at least one of a power characteristic and a frequency characteristic of at least one of the processor cores. The control circuitry can determine that a frequency control opportunity is present on at least one of the processor cores based on at least one of the power characteristic and the frequency characteristic. The control circuitry can adjust a power parameter of at least one of the processor cores responsive to determining that the frequency control opportunity is present.

US Patent:

20210390232, Dec 16, 2021

Filed:

Apr 30, 2021

Appl. No.:

17/245000

Inventors:

- Dallas TX, US
Sreenivasan K. KODURI - Dallas TX, US
Nikhil GUPTA - Plano TX, US
Timothy W. FISCHER - McKinney TX, US

International Classification:

G06F 30/27
G06N 3/08
G06F 30/392
G06F 30/398

Abstract:

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

US Patent:

20210390233, Dec 16, 2021

Filed:

Apr 30, 2021

Appl. No.:

17/245083

Inventors:

- Dallas TX, US
Nikhil GUPTA - Plano TX, US
Sreenivasan K. KODURI - Dallas TX, US
Timothy W. FISCHER - McKinney TX, US

International Classification:

G06F 30/27
G06N 3/08
G06F 30/392
G06F 30/398
G06F 30/337

Abstract:

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

US Patent:

20210390237, Dec 16, 2021

Filed:

Apr 30, 2021

Appl. No.:

17/245253

Inventors:

- Dallas TX, US
Sreenivasan K. KODURI - Dallas TX, US
Nikhil GUPTA - Plano TX, US
Timothy W. FISCHER - McKinney TX, US

International Classification:

G06F 30/3308
G06F 30/367
G06F 30/373
G06N 3/08
G06N 20/20

Abstract:

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

US Patent:

20210390239, Dec 16, 2021

Filed:

Apr 30, 2021

Appl. No.:

17/245057

Inventors:

- Dallas TX, US
Sreenivasan K. KODURI - Dallas TX, US
Nikhil GUPTA - Plano TX, US
Timothy W. FISCHER - McKinney TX, US

International Classification:

G06F 30/392
G06N 3/08
G06N 3/04

Abstract:

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

US Patent:

20210390243, Dec 16, 2021

Filed:

Apr 30, 2021

Appl. No.:

17/245022

Inventors:

- Dallas TX, US
Ashish KHANDELWAL - Irving TX, US
Sreenivasan K. KODURI - Dallas TX, US
Nikhil GUPTA - Plano TX, US

International Classification:

G06F 30/398
G06F 30/392

Abstract:

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

US Patent:

20200125389, Apr 23, 2020

Filed:

Nov 8, 2019

Appl. No.:

16/678888

Inventors:

Stephen T. Palermo - Chandler AZ, US
Nikhil Gupta - Portland OR, US
Vasudevan Srinivasan - Portland OR, US
Christopher MacNamara - Limerick, IE
Sarita Maini - Santa Clara CA, US
Abhishek Khade - Chandler AZ, US
Edwin Verplanke - Chandler AZ, US
Lokpraveen Mosur - Santa Clara CA, US

International Classification:

G06F 9/455
G06F 9/50

Abstract:

Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.