Norma Jeanette Rodriguez

US Patent:

20080148211, Jun 19, 2008

Filed:

Dec 19, 2006

Appl. No.:

11/613006

Inventors:

Vito Dai - Santa Clara CA, US
Jie Yang - Sunnyvale CA, US
Norma Rodriguez - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 9/455

US Classification:

716 11

Abstract:

Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.