Norman L Culp

US Patent:

6836148, Dec 28, 2004

Filed:

May 8, 2002

Appl. No.:

10/141297

Inventors:

Donald T. Pullen - Anaheim CA
Norman L. Culp - Plano TX
Xiaoyu Xi - Plano TX
Keith E. Kunz - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 190185

US Classification:

326 81, 326 83, 326 68, 327333, 327427, 327434

Abstract:

A output driver architecture ( ) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator ( ), level shifter ( ) and output stage ( ) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage. Further, the bias generator is adapted to sense the magnitude of the high voltage supply, and to automatically and continuously self-adjust the bias voltage in response to changes sensed in the magnitude of the high voltage supply such that the bias generator can be used for a continuous range of high voltage supplies up to 6 times the normal operating voltage of the transistors.

US Patent:

7400064, Jul 15, 2008

Filed:

Apr 22, 2005

Appl. No.:

11/112266

Inventors:

Siew Kuok Hoon - Dallas TX, US
Norman L. Culp - Montgomery TX, US
Jun Chen - Allen TX, US
Franco Maloberti - Torre D'Isola, IT

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02J 1/00
G05F 1/56
H02M 3/335

US Classification:

307 39, 307 31, 323284, 363 2111, 363 2117, 363 2118, 363 25

Abstract:

A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.

US Patent:

7474582, Jan 6, 2009

Filed:

Dec 12, 2006

Appl. No.:

11/637352

Inventors:

Hugh Thomas Mair - Fairview TX, US
James Sangwon Song - Plano TX, US
Franck Benjamin Dahan - Nice, FR
William Douglas Wilson - Dallas TX, US
Norman LeRoy Culp - Dallas TX, US
Sudha Thiruvengadam - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 5/14
G11C 11/00
G11C 7/06

US Classification:

365226, 365154, 36518907, 36518909

Abstract:

One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.

US Patent:

20140042959, Feb 13, 2014

Filed:

Oct 16, 2012

Appl. No.:

13/653244

Inventors:

Norman L. Culp - Montgomery TX, US

International Classification:

H02J 7/00

US Classification:

320107, 320162

Abstract:

A battery charger and system and method for use of the same are disclosed for increasing a charge of a battery. In one embodiment of the battery charger, an input for an electric charging power source is configured to supply electrical charging power to a rechargeable battery via an output circuit portion interposed therebetween. A transfer function circuit portion is configured to sense the voltage of the rechargeable battery as a sensing voltage such that the change in the sensing voltage is directly proportional to the internal impedance of the rechargeable battery. A control logic circuit portion is configured to select between a constant current, variable voltage operational mode, a constant current, scalable voltage operational mode, and a variable current, constant voltage operational mode to furnish rapid recharging of the rechargeable battery.

US Patent:

20140042960, Feb 13, 2014

Filed:

Aug 8, 2013

Appl. No.:

13/962661

Inventors:

Norman L. Culp - Montgomery TX, US

International Classification:

H02J 7/00

US Classification:

320107, 320162

Abstract:

A battery charger and system and method for use of the same are disclosed for increasing a charge of a battery. In one embodiment of the battery charger, an input for an electric charging power source is configured to supply electrical charging power to a rechargeable battery via an output circuit portion interposed therebetween. A transfer function circuit portion is configured to sense the voltage of the rechargeable battery as a sensing voltage such that the change in the sensing voltage is directly proportional to the internal impedance of the rechargeable battery. A control logic circuit portion is configured to select between a constant current, variable voltage operational mode, a constant current, scalable voltage operational mode, and a variable current, constant voltage operational mode to furnish rapid recharging of the rechargeable battery.

US Patent:

61211044, Sep 19, 2000

Filed:

Dec 12, 1997

Appl. No.:

9/301410

Inventors:

Eugene G. Dierschke - Dallas TX
Norman Culp - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218234
H01L 218244
H01L 2120

US Classification:

438382

Abstract:

An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration overlying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

US Patent:

60052805, Dec 21, 1999

Filed:

Dec 12, 1997

Appl. No.:

8/989610

Inventors:

Eugene G. Dierschke - Dallas TX
Norman Culp - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257528

Abstract:

An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration over-lying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

US Patent:

52818608, Jan 25, 1994

Filed:

Dec 21, 1992

Appl. No.:

7/994433

Inventors:

William R. Krenik - Garland TX
Norman L. Culp - Monument CO
Chih-Hung Lin - Xin Dian City, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1776
H03K 500

US Classification:

307243

Abstract:

A method and apparatus for an improved multiple channel sensor interface circuit is described which comprises a plurality of input integrator circuits (35) coupled in parallel; a switched capacitor multiplexer (37) coupled to the input integrator circuits (35); and an output integrator stage (39) coupled to the switched capacitor multiplexer (37). An additional embodiment is described wherein a multiple channel voltage sensor interface circuit comprising a plurality of switched capacitor storage elements (S26. . . S28) is coupled to a plurality of inputs; a plurality of integrator amplifiers (51, 53) is coupled to the switched capacitor storage elements (C22. . . C30); and timing circuitry is coupled to the switched capacitor storage elements (C221. . . C30) and to integrator amplifiers (51, 53) operable to selectively enable sampling of the inputs.