Ohad O Falik from 1035 Aster Ave, Sunnyvale, CA 94086, age 61

System For Sending And Receiving Data On A Universal Serial Bus (Usb) Using A Memory Shared Among A Number Of End Points
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US Patent:

61450456, Nov 7, 2000
Filed:

Jan 7, 1998
Appl. No.:

9/004003
Inventors:

Ohad Falik - Sunnyvale CA
David Brief - Raanana, IL
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F 1314
US Classification:

710129
Abstract:

An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of endpoints are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.

System For Sending And Receiving Data On A Universal Serial Bus (Usb) Using A Memory Shared Among A Number Of Endpoints
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US Patent:

61733555, Jan 9, 2001
Filed:

Dec 22, 1999
Appl. No.:

9/469663
Inventors:

Ohad Falik - Sunnyvale CA
David Brief - Ra'anana, IL
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F 1314
US Classification:

710129
Abstract:

An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of end points are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.

Multi-Processor Element Provided With Hardware For Software Debugging
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US Patent:

60650788, May 16, 2000
Filed:

Jun 11, 1998
Appl. No.:

9/096402
Inventors:

Ohad Falik - Sunnyvale CA
Ophir Shabtay - Haifa, IL
Gideon Intrater - Sunnyvale CA
Tzvia Weisman - Shoham, IL
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

G06F 1300
US Classification:

710100
Abstract:

A multiprocessor system includes a plurality of processors. A debugger interface includes interface circuitry to interface the plurality of processors to a debugger. The debugger interface includes means for receiving a debugger command from the debugger. Debugger command directing means determines from the debugger command for which of at least one of the plurality of processors the debugger command is intended, directs the debugger command, via the interface circuitry to the at least one intended processor. A processor command is received from one of the plurality of processors, and processor command directing means directs the processor command, received from the one processor, via the interface circuitry to the debugger. The system is especially suited for debugging software that is executing on the plurality of processors of the multiprocessor system.

Ohad O Falik