Olivier F Garreau

US Patent:

6425101, Jul 23, 2002

Filed:

Oct 30, 1998

Appl. No.:

09/183620

Inventors:

Olivier Garreau - Santa Clara CA

Assignee:

Infineon Technologies North America Corp. - San Jose CA

International Classification:

G01R 3128

US Classification:

714727

Abstract:

An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network.