Omar M Shaikh

US Patent:

20130262838, Oct 3, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/435165

Inventors:

Muawya M. Al-Otoom - Beaverton OR, US
Paul Caprioli - Hillsboro OR, US
Abhay S. Kanhere - Fremont CA, US
Arvind Krishnaswamy - San Jose CA, US
Omar M. Shaikh - Portland OR, US

International Classification:

G06F 9/30

US Classification:

712225, 712E09016

Abstract:

A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.

US Patent:

20130305019, Nov 14, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/996352

Inventors:

Paul Caprioli - Hillsboro OR, US
Martin G. Dixon - Portland OR, US
Brett L. Toll - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US
Omar M. Shaikh - Portland OR, US

International Classification:

G06F 9/30

US Classification:

712205

Abstract:

A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.

US Patent:

20130311758, Nov 21, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/993792

Inventors:

Paul Caprioli - Hillsboro OR, US
Matthew C. Merten - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US
Omar M. Shaikh - Portland OR, US
Abhay S. Kanhere - Fremont CA, US
Suresh Srinivas - Portland OR, US
Koichi Yamada - Los Gatos CA, US
Vivek Thakkar - Sunnyvale CA, US
Pawel Osciak - Santa Clara CA, US

International Classification:

G06F 9/38

US Classification:

712233

Abstract:

A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

US Patent:

20110167416, Jul 7, 2011

Filed:

Dec 25, 2010

Appl. No.:

12/978557

Inventors:

David J. Sager - Portland OR, US
Ruchira Sasanka - Hillsboro OR, US
Ron Gabor - Ra'anana, IL
Shlomo Raikin - Geva Carmel, IL
Joseph Nuzman - Haifa, IL
Leeor Peled - Haifa, IL
Jason A. Domer - Hillsboro OR, US
Ho-Seop Kim - Portland OR, US
Youfeng Wu - Palo Alto CA, US
Koichi Yamada - Los Gatos CA, US
Howard H. Chen - Sunnyvale CA, US
Jayaram Bobba - Portland OR, US
Jeffery J. Cook - Hillsboro OR, US
Omar M. Shaikh - Portland OR, US
Suresh Srinivas - Portland OR, US

International Classification:

G06F 9/45

US Classification:

717149

Abstract:

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

US Patent:

20180060049, Mar 1, 2018

Filed:

Jun 6, 2017

Appl. No.:

15/615798

Inventors:

- Santa Clara CA, US
RUCHIRA SASANKA - Hillsboro OR, US
RON GABOR - Hertzliya, IL
SHLOMO RAIKIN - Moshav Sde Eliezer, IL
JOSEPH NUZMAN - Haifa, IL
LEEOR PELED - Haifa, IL
JASON A. DOMER - Hillsboro OR, US
HO-SEOP KIM - Portland OR, US
YOUFENG WU - Palo Alto CA, US
KOICHI YAMADA - Los Gatos CA, US
HOWARD H. CHEN - Sunnyvale CA, US
JAYARAM BOBBA - Portland OR, US
JEFFREY J. COOK - Portland OR, US
OMAR M. SHAIKH - Portland OR, US
SURESH SRINIVAS - Portland OR, US

International Classification:

G06F 9/45
G06F 11/36
G06F 9/38
G06F 9/54

Abstract:

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

US Patent:

20170212825, Jul 27, 2017

Filed:

Jan 10, 2017

Appl. No.:

15/403120

Inventors:

- Santa Clara CA, US
Matthew C. Merten - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US
Omar M. Shaikh - Portland OR, US
Abhay S. Kanhere - Fremont CA, US
Suresh Srinivas - Portland OR, US
Koichi Yamada - Los Gatos CA, US
Vivek Thakkar - Sunnyvale CA, US
Pawel Osciak - Santa Clara CA, US

International Classification:

G06F 11/34
G06F 9/455
G06F 11/36
G06F 11/07
G06F 9/45

Abstract:

A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

US Patent:

20170097826, Apr 6, 2017

Filed:

Dec 16, 2016

Appl. No.:

15/382476

Inventors:

Omar M. Shaikh - Portland OR, US
Ravi Rajwar - Portland OR, US
Paul Caprioli - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US

International Classification:

G06F 9/38
G06F 9/46
G06F 12/084
G06F 9/30
G06F 12/0875

Abstract:

Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

US Patent:

20170097891, Apr 6, 2017

Filed:

Dec 16, 2016

Appl. No.:

15/382462

Inventors:

Omar M. Shaikh - Portland OR, US
Ravi Rajwar - Portland OR, US
Paul Caprioli - Hillsboro OR, US
Muawya M. Al-Otoom - Beaverton OR, US

International Classification:

G06F 12/0817
G06F 12/0842
G06F 9/38
G06F 11/14
G06F 9/46
G06F 9/30
G06F 12/084
G06F 12/0875

Abstract:

Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.