Qualcomm May 2009 - Apr 2012
Asic and Phy Design Engineer
Qualcomm May 2009 - Apr 2012
Staff Asic Design Engineer at Qualcomm
University of Southern California Dec 2008 - May 2009
Grading Assistant
Evalueserve Aug 2006 - Aug 2007
Research Associate
Education:
University of Southern California 2007 - 2009
Master of Science, Masters, Computer Engineering
Department of Technology, Savitribai Phule Pune University 2002 - 2006
Bachelor of Engineering, Bachelors, Electronics
Skills:
Verilog Asic Synopsys Tools Xilinx Cadence Virtuoso Integrated Circuit Design Vhdl Dft Tcl Computer Architecture Fpga Perl Script Digital Ic Design Process Engineering Static Timing Analysis Rtl Design System V Synopsys Primetime Phy High Speed Digital Design Low Power Systems Memory Perl Automation Cadence Virtuoso Xl Applied Physics Silicon Validation System Architecture Functional Verification Perl Field Programmable Gate Arrays Application Specific Integrated Circuits Very Large Scale Integration Drc