Partha Partha Srinivasan

US Patent:

60024410, Dec 14, 1999

Filed:

Oct 28, 1996

Appl. No.:

8/742583

Inventors:

Hemant Bheda - Cupertino CA
Ygal Arbel - Belmont CA
Partha Srinivasan - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara

International Classification:

H04N 732

US Classification:

348423

Abstract:

A novel method and apparatus for decoding a compressed audio/video signal to produce decoded audio and decoded video signals. The decoding tasks are partitioned into "pre-processing tasks" and "post-processing tasks. " Pre-processing tasks involve one or more non-signal processing oriented operations which do not require extensive computing resources. Pre-processing tasks are assigned to be executed by the host processor, which can perform these tasks without straining it computational resources. Pre-processing tasks include demultiplexing the compressed audio/video stream into compressed audio and compressed video streams, performing audio pre-processing on the compressed audio stream and performing video pre-processing on the compressed video stream. Post-processing tasks involve one or more signal processing oriented operations which require extensive computing resources. Pre-processing tasks are assigned to be executed by a dedicated subprocessor.

US Patent:

59909587, Nov 23, 1999

Filed:

Jun 17, 1997

Appl. No.:

8/877136

Inventors:

Hemant Bheda - Cupertino CA
Sanjay Gongalore - Cupertino CA
Partha Srinivasan - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H04N 718

US Classification:

348407

Abstract:

A novel apparatus and method is disclosed to decode an encoded MPEG video stream in an efficient manner making optimal use of available system memory and computational resources. The present invention partitions the MPEG video decode task into software tasks which are executed by a CPU and hardware tasks which are implemented in dedicated video hardware. Software tasks represent those tasks which do not require extensive memory or computational resources. On the other hand, tasks implemented in dedicated video hardware represent those tasks which involve computational and memory mintensive operations. Synchronization between software tasks executed by the CPU and hardware tasks implemented in dedicated video hardware is achieved by means of various data structures, control structures and device drivers.

US Patent:

57816646, Jul 14, 1998

Filed:

Oct 10, 1997

Appl. No.:

8/949019

Inventors:

Hemant Bheda - Cupertino CA
Partha Srinivasan - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06K 936

US Classification:

382233

Abstract:

A novel method and structure for the implementation of Half Pixel Filtering and Block Averaging that are efficient for implementation on a general purpose CPU. The number of required operations are reduced by operating on multiple pixels simultaneously using sliced arithmetic, while maintaining full accuracy. In certain embodiments, the number of operations are further reduced by compromising full accuracy. This approximation is applicable to decoding of bi-directional frames.

US Patent:

51877961, Feb 16, 1993

Filed:

Jul 16, 1990

Appl. No.:

7/553884

Inventors:

Yulun Wang - Goleta CA
Partha Srinivasan - Goleta CA

Assignee:

Computer Motion, Inc. - Goleta CA

International Classification:

G06F 15347

US Classification:

395800

Abstract:

The present invention is a three-dimensional vector co-processing system (3DVCP) including the datapath of a three-dimensional vector co-processor having a register-to-register architecture and being coupled to a general-purpose processor. The source multiplexer and the destination multiplexer of the co-processor uses full cross-bar switches. As such, the three-dimensional co-processor evaluates three-dimensional vectors and scalars while the general-purpose processor performs the other "general purpose" functions. The 3DVCP includes a co-processor interface for synchronizing the three-dimensional vector co-processor and the general-purpose processor. With this interface, the general-purpose processor controls the address bus and control lines of the data bus. The three-dimensional vector co-processor also has an instruction set that enables the control unit to pipeline the program instructions in stages in addition to instruction fetch, fetch instruction, instruction execute, and store-result. The 3DVCP specifically targets vectors of length 3, and expoits the intrinsic parallelism by providing three parallel execution units that can simultaneously operate on all three vector components.