Pascal Chauvet
age ~53
from Berkeley, CA
- Also known as:
-
- Pascal Pascal
- Phone and address:
-
533 Spruce St, Berkeley, CA 94707
4158217659
Pascal Chauvet Phones & Addresses
- 533 Spruce St, Berkeley, CA 94707 • 4158217659
- 228 Poplar Ave, San Mateo, CA 94401 • 6506856568
- 975 Palm Ave, San Mateo, CA 94401 • 6506856568
- Oakland, CA
- 460 3Rd St, San Jose, CA 95112
- 3901 26Th St, San Francisco, CA 94131 • 4158217659
- Santa Clara, CA
Work
-
Company:MagillemOct 2015
-
Position:Vp, strategic accounts
Education
-
Degree:Master of Science, Masters
-
School / High School:Conservatoire National Des Arts Et Métiers
-
Specialities:Electrical Engineering, Architecture
Skills
Soc • Eda • System Architecture • Systemc • Semiconductors • Asic • Embedded Systems • Debugging • Verilog • Hardware Architecture • C • Product Management • Arm • Simulations • Embedded Software • Ip • Vhdl • Perl • Microprocessors • Computer Architecture • Algorithms • Fpga • Device Drivers • Application Specific Integrated Circuits • C++ • Processors • Technical Marketing • Field Programmable Gate Arrays • Java • Python • Rtl Design • Ip Xact • Management • French • Business Development • Consultative Selling • Solutions Marketing • Sales Operations • Pre Sales
Languages
English • French
Industries
Semiconductors
Resumes
Vp, Strategic Accounts
view sourceLocation:
533 Spruce St, Berkeley, CA 94707
Industry:
Semiconductors
Work:
Magillem
Vp, Strategic Accounts
Magillem Apr 2013 - Sep 2015
Vice President of Technical Marketing
Sonics, Inc. Oct 2006 - Mar 2013
Application Architect, Digital Consumer
Coware Oct 2005 - Oct 2006
Solution Marketing Specialist
Coware Oct 2004 - Sep 2005
Technical Marketing Manager
Vp, Strategic Accounts
Magillem Apr 2013 - Sep 2015
Vice President of Technical Marketing
Sonics, Inc. Oct 2006 - Mar 2013
Application Architect, Digital Consumer
Coware Oct 2005 - Oct 2006
Solution Marketing Specialist
Coware Oct 2004 - Sep 2005
Technical Marketing Manager
Education:
Conservatoire National Des Arts Et Métiers
Master of Science, Masters, Electrical Engineering, Architecture
Master of Science, Masters, Electrical Engineering, Architecture
Skills:
Soc
Eda
System Architecture
Systemc
Semiconductors
Asic
Embedded Systems
Debugging
Verilog
Hardware Architecture
C
Product Management
Arm
Simulations
Embedded Software
Ip
Vhdl
Perl
Microprocessors
Computer Architecture
Algorithms
Fpga
Device Drivers
Application Specific Integrated Circuits
C++
Processors
Technical Marketing
Field Programmable Gate Arrays
Java
Python
Rtl Design
Ip Xact
Management
French
Business Development
Consultative Selling
Solutions Marketing
Sales Operations
Pre Sales
Eda
System Architecture
Systemc
Semiconductors
Asic
Embedded Systems
Debugging
Verilog
Hardware Architecture
C
Product Management
Arm
Simulations
Embedded Software
Ip
Vhdl
Perl
Microprocessors
Computer Architecture
Algorithms
Fpga
Device Drivers
Application Specific Integrated Circuits
C++
Processors
Technical Marketing
Field Programmable Gate Arrays
Java
Python
Rtl Design
Ip Xact
Management
French
Business Development
Consultative Selling
Solutions Marketing
Sales Operations
Pre Sales
Languages:
English
French
French
Us Patents
-
Method And System For A Database To Monitor And Analyze Performance Of An Electronic Design
view source -
US Patent:8073820, Dec 6, 2011
-
Filed:Apr 7, 2008
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Appl. No.:12/098614
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Inventors:Krishnan Srinivasan - Cupertino CA, US
Chien-Chun Chou - Saratoga CA, US
Pascal Chauvet - San Mateo CA, US -
Assignee:Sonics, Inc. - Milpitas CA
-
International Classification:G06F 7/00
G06F 17/00
G06F 17/50 -
US Classification:707688, 703 14
-
Abstract:Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between initiator intellectual property (IP) cores and target IP cores of the electronic design. A query tool may be configured to format input data to be stored in the defined tables, and have application programming interfaces to retrieve data from the defined tables based on performing a query. The query tool executes an algorithm based on the query to provide the interconnect analysis.
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Method And System To Monitor, Debug, And Analyze Performance Of An Electronic Design
view source -
US Patent:20100057400, Mar 4, 2010
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Filed:Sep 4, 2008
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Appl. No.:12/204156
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Inventors:Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Drew E. Wingard - Palo Alto CA, US
Pascal Chauvet - San Mateo CA, US -
Assignee:Sonics, Inc. - Milpitas CA
-
International Classification:G21C 17/00
-
US Classification:702182
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Abstract:Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.
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