Patrick Timothy Codd

US Patent:

20060067031, Mar 30, 2006

Filed:

Sep 24, 2004

Appl. No.:

10/948638

Inventors:

Stanford Crane - San Jose CA, US
Zsolt Horvath - Millbrae CA, US
Josh Nickel - San Jose CA, US
Myoung-soo Jeon - Fremont CA, US
Charley Ogata - San Jose CA, US
Vincent Alcaria - Manteca CA, US
Patrick Codd - Palo Alto CA, US

International Classification:

H01G 4/228

US Classification:

361306200

Abstract:

A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.

US Patent:

20060279904, Dec 14, 2006

Filed:

Aug 21, 2006

Appl. No.:

11/506909

Inventors:

Stanford Crane - San Jose CA, US
Zsolt Horvath - Millbrae CA, US
Josh Nickle - San Jose CA, US
Myoung-soo Jeon - Fremont CA, US
Charley Ogata - San Jose CA, US
Vincent Alcaria - Manteca CA, US
Patrick Codd - Palo Alto CA, US

International Classification:

H01G 4/228
H01G 7/00

US Classification:

361306200, 029025410, 029831000, 029837000

Abstract:

A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.

US Patent:

20180219310, Aug 2, 2018

Filed:

Jan 27, 2017

Appl. No.:

15/417772

Inventors:

- Redmond WA, US
Hanfeng Wang - San Jose CA, US
Joseph Christopher Bolling - San Francisco CA, US
Patrick Timothy Codd - Belmont CA, US

International Classification:

H01R 12/52
H01R 13/02
H01B 11/18
H05K 1/11
H05K 1/14
H01R 24/50

Abstract:

In an electronic device having a compact form factor, such as a head mounted display (HMD) device, a space-saving harness using bundled or ribbonized strands of micro-coaxial (micro-coax) cable may be utilized to provide signal and/or power interconnects between EMI-generating peripheral components and other components in the device such as those populated on circuit boards. Discrete wires are included in the harness to provide shielding to adjacent micro-coax conductors which may carry high speed signals such as MIPI (Mobile Industry Processor Interface) differential signal pairs and provide power and ground return paths. The discrete wires are subjected to fabrication processes during assembly of the micro-coax harness so that their outer diameters substantially match that of components in the micro-coax cable to thereby facilitate connectorization or termination to the circuit boards and/or other components in the device. The matching outer diameters can also provide a consistent pitch (i.e., spacing between adjacent micro-coax cables and discrete wires) that may facilitate space-saving geometries for the harness, connector, and/or terminations.

US Patent:

20170295642, Oct 12, 2017

Filed:

Apr 11, 2016

Appl. No.:

15/095581

Inventors:

Patrick Codd - Belmont CA, US
Agustya Mehta - Mountain View CA, US

International Classification:

H05K 1/02
H05K 1/14
G02B 27/01
H05K 1/11

Abstract:

In an electronic device having a compact form factor, such as a head mounted display device, flexible printed circuits may be utilized to provide interconnects between EMI-generating peripheral components and other components in the device such as those populated on main circuit boards. Coverlays utilized to protect circuit traces and ground planes in the flexible printed circuits are configured with openings that can expose ground planes at various locations throughout the electronic device. Electrical pathways are formed by conductive foam, conductive adhesives, and/or other conductive materials between the exposed ground planes and a device ground to establish multiple ground loops throughout the device that shunt EMI energy that is generated by electronic components and circuits during device operation. The coverlay openings can be positioned on the flexible printed circuits so that the lengths of the ground loops are minimized to enhance overall EMI emission management performance.

US Patent:

20170273171, Sep 21, 2017

Filed:

Mar 16, 2016

Appl. No.:

15/071481

Inventors:

Patrick Codd - Belmont CA, US
Agustya Mehta - Mountain View CA, US

International Classification:

H05K 1/02
H04N 5/225
H04N 5/357

Abstract:

In an electronic device that employs high-speed differential signaling on one or more pairs of conductors in a flexible printed circuit, RF chokes are placed in the differential signal path and mounted directly on the flexible printed circuit which is used to interconnect a peripheral device, such as an image sensor, through a connector to another device component such as a main printed circuit board. The RF chokes are configured to suppress common-mode noise propagating in the differential pairs of conductors. In one illustrative embodiment, the RF chokes are located on the flexible printed circuit adjacent to the peripheral device to suppress common-mode noise near its source. In another illustrative embodiment, the RF chokes are mounted adjacent to the connector to suppress the common-mode noise before it has an opportunity to escape the flexible printed circuit at the major discontinuity presented by the connector.

US Patent:

20160165728, Jun 9, 2016

Filed:

Dec 9, 2014

Appl. No.:

14/565360

Inventors:

Scott Francis Fullam - Palo Alto CA, US
Patrick Timothy Codd - Belmont CA, US
Agustya Ruchir Mehta - Mountain View CA, US

International Classification:

H05K 1/18
H05K 1/02

Abstract:

Embodiments are disclosed for a printed circuit board. An example printed circuit board includes a ground plane comprising a pattern of an electrically conductive material. The example printed circuit board further includes a circuit trace disposed adjacent to the ground plane, where one or more characteristics of one of more of the pattern of the electrically conductive material in the ground plane and the circuit trace vary based upon a directional change of the circuit trace.