Patrick J Conway

US Patent:

6742101, May 25, 2004

Filed:

May 21, 2002

Appl. No.:

10/153480

Inventors:

Sudheer Miryala - San Jose CA
Jeremy J. Farrell - Campbell CA
Kazunori Masuyama - Kanazawa, JP
Patrick N. Conway - Los Altos CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 1210

US Classification:

711202, 711220, 711221, 709245

Abstract:

A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.

US Patent:

6754776, Jun 22, 2004

Filed:

May 17, 2001

Appl. No.:

09/861258

Inventors:

Patrick N. Conway - Los Altos CA
Kazunori Masuyama - San Jose CA
Takeshi Shimizu - San Jose CA
Toshio Ogawa - San Jose CA
Martin Sodos - San Jose CA
Sudheer Miryala - San Jose CA
Jeremy Farrell - Campbell CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 1200

US Classification:

711129, 711 3, 711128, 711153, 711173

Abstract:

A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.

US Patent:

6766360, Jul 20, 2004

Filed:

Jul 14, 2000

Appl. No.:

09/616583

Inventors:

Patrick N. Conway - Los Altos CA
Yukihiro Nakagawa - Cupertino CA
Jung Rung Jiang - Cupertino CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 15167

US Classification:

709214, 709104, 709212, 709215, 709216, 709217, 711121, 711130, 711141, 711200

Abstract:

A computer network system for manipulating requests for shared data includes a plurality of groups and each group has a plurality of nodes and each node has a plurality of processors. The system further comprises a request outstanding buffer (ROB) for recording data requests, a remote access cache (RAC) for caching the results of prior memory requests which are remote to a requesting node, and a directory for recording a global state of a cache line in the system. The RAC supports only two states, Shared and Invalid, and caches only clean remote data. If the directory state is Modified/Exclusive, the line is indicated to not be in the RAC. The behavior of the RAC is described for two important cases: initial RAC does not have the line caches and initial RAC has the line cached. The requested data is supplied to the requesting node from the RAC when the RACs line is cached and when the RACs line is not cached, the requested data is supplied from the remote home node and the requested data is installed in the RAC. In the case when the data is not present in the RAC, the request to the remote home node is overlapped with the RAC access to minimize remote memory access latency.

US Patent:

6862634, Mar 1, 2005

Filed:

May 17, 2002

Appl. No.:

10/150276

Inventors:

Jeremy J. Farrell - Campbell CA, US
Kazunori Masuyama - Kanazawa, JP
Sudheer Miryala - San Jose CA, US
Patrick Conway - Los Altos CA, US

Assignee:

Fujitsu Limited - Kanagawa

International Classification:

G06F003/00

US Classification:

710 38, 709201, 709223, 712 32

Abstract:

In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i. e. , it does not rely on immediately preceding write to determine where the data packet should be sent. Using “address aliasing”, CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.

US Patent:

6868485, Mar 15, 2005

Filed:

Sep 27, 2002

Appl. No.:

10/256318

Inventors:

Patrick Conway - Los Altos CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F012/00

US Classification:

711154, 711156, 711145, 711144, 711128, 711129, 711170, 709218

Abstract:

A computer system with an integrated directory and processor cache. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of cache memory subsystem, such as an L2 cache, associated with a processor core. In one particular implementation, directory entries are stored within the cache memory subsystem to provide indications of lines (or blocks) that may be cached in modified, exclusive, or owned coherency states. The absence of a directory entry for a particular line may imply that the line is cached in either shared or invalid states.

US Patent:

6961761, Nov 1, 2005

Filed:

May 17, 2001

Appl. No.:

09/861293

Inventors:

Kazunori Masuyama - San Jose CA, US
Patrick N. Conway - Los Altos CA, US
Hitoshi Oi - San Jose CA, US
Jeremy Farrell - Campbell CA, US
Sudheer Miryala - San Jose CA, US
Yukio Nishimura - Cupertino CA, US
Prabhu Murthy - San Jose CA, US

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F015/177

US Classification:

709220, 709229, 709221, 709222, 710 8, 710 14

Abstract:

A domain partitioning system for a multi-node computer system is disclosed. An external server manager is coupled to a domain configuration unit by a dedicated sideband channel. The server manager has write privileges to the domain configuration unit that allows the server manager to control the domain partitioning and the routing tables. None of the domains of the computer system are permitted write access to the domain configuration unit. In one embodiment, the domain configuration unit is a set of domain partition registers and routing table registers coupled to a system interconnect.

US Patent:

7062610, Jun 13, 2006

Filed:

Sep 30, 2002

Appl. No.:

10/261642

Inventors:

Patrick Conway - Los Altos CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711141

Abstract:

A data processor () recognizes a special data processing operation in which data will be stored in a cache () for one use only. The data processor () allocates a memory location to at least one cache line of the cache (). A data producer such as a data communication driver program running on a central processing unit () then writes a data element to the allocated memory location. A data consumer () reads the data element by sending a READ ONCE request to a host bridge (). The host bridge () provides the READ ONCE request to a memory controller (), which reads the data from the cache () and de-allocates the at least one cache line without performing a writeback from the cache to a main memory (). In one form the memory controller () de-allocates the at least one cache line by issuing a probe marking the next state of the associated cache line as invalid.

US Patent:

7096323, Aug 22, 2006

Filed:

Sep 27, 2002

Appl. No.:

10/256970

Inventors:

Patrick Conway - Los Altos CA, US
Frederick D. Weber - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 13/14

US Classification:

711147, 711144, 711129, 711130, 711156, 709218, 709232

Abstract:

A computer system with a processor cache that stores remote cache presence information. In one embodiment, a plurality of presence vectors are stored to indicate whether particular blocks of data mapped to another node are being remotely cached. Rather than storing the presence vectors in a dedicated storage, the remote cache presence vectors may be stored in designated locations of a cache memory subsystem, such as an L cache, associated with a processor core. For example, a designated way of the cache memory subsystem may be allocated for storing remote cache presence vectors, while the remaining ways of the cache are used to store normal processor data. New data blocks may be remotely cached in response to evictions from the cache memory subsystem. In yet a further embodiment, additional entries of the cache memory subsystem may be used for storing directory entries to filter probe command and response traffic.