Patrick J Devaney

US Patent:

20040177224, Sep 9, 2004

Filed:

Mar 7, 2003

Appl. No.:

10/384198

Inventors:

Patrick Devaney - Haverhill MA, US
David M. Keaton - Boulder CO, US
Katsumi Murai - Moriguchi-City, JP

International Classification:

G06F012/00

US Classification:

711/148000, 711/151000

Abstract:

A multiprocessor system for concurrently executing multiple tasks includes first and second processors, each configured to execute at least one task and a local memory physically disposed externally of, and concurrently accessible by the first and second processors. An operating system assigns: (a) a first task to the first processor and a second task to the second processor, the first and second tasks having respective execution resource requirements, (b) a first portion of the local memory to the first processor, and (c) a second portion of the local memory to the second processor. The operating system is configured to initially adjust the first and second portions of the local memory based on the respective execution resource requirements. Portions of the local memory assigned to be shared by the first and second processors may be cooperatively accessed by each of the processors without intervention by the operating system.

US Patent:

20040193668, Sep 30, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/403315

Inventors:

Patrick Devaney - Haverhill MA, US
David Keaton - Boulder CO, US
Katsumi Murai - Moriguchi-City, JP

International Classification:

G06F007/38

US Classification:

708/523000

Abstract:

A processing system includes left and right data path processors configured to concurrently receive parallel instructions. Left and right accumulators which are, respectively, disposed in the left and right data path processors, are configured to execute an accumulate instruction and obtain an accumulation value. Left and right local memories (LMs) are coupled to the left and right accumulators and configured to store the accumulation value. The accumulation value is equally divided for storage in the left LM and the right LM.

US Patent:

20040193835, Sep 30, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/403209

Inventors:

Patrick Devaney - Haverhill MA, US
David Keaton - Boulder CO, US
Katsumi Murai - Moriguchi-City, JP

International Classification:

G06F012/00

US Classification:

711/220000

Abstract:

In a processor system configured to execute instructions, a method finds an entry in at least one table stored in memory. The method includes (a) storing a first table of multiple entries, each entry including a bit field; (b) storing (i) a first entry of the first table and (ii) a bit size of each entry; (c) storing a sequence of data bits; (d) selecting a portion of the sequence of data bits to produce a data field having a bit size same as the bit size of each entry in the first table; and (e) adding the first entry of the first table to the produced data field to find the entry in the first table.

US Patent:

20040193837, Sep 30, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/403216

Inventors:

Patrick Devaney - Haverhill MA, US
David Keaton - Boulder CO, US
Katsumi Murai - Moriguchi-City, JP

International Classification:

G06F015/00

US Classification:

712/003000

Abstract:

A data processing system includes left and right data path processors coupled to an instruction cache. The left and right data path processors, respectively, are configured to execute left and right instruction words received in a single clock cycle from the instruction cache. The left and right data path processors are also configured to operate in a scalar mode and a vector mode. The processors (a) execute the left and right instruction words as two separate instructions in the scalar mode, and (b) execute the left and right instruction words as one instruction in the vector mode.

US Patent:

20040193838, Sep 30, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/403241

Inventors:

Patrick Devaney - Haverhill MA, US
David M. Keaton - Boulder CO, US
Katsumi Murai - Moriguchi-City, JP

International Classification:

G06F015/00

US Classification:

712/003000

Abstract:

A processing system includes left and right data path processors configured to execute instructions issued from an instruction cache. A vector instruction includes a first word configured for execution by the left data path processor and a second word configured for execution by the right data path processor. The first and second words are issued in the same clock cycle from the instruction cache, and are interlocked to jointly specify a single vector instruction. The first and second words include code for vector operation and code for vector control. The first and second words are concurrently executed to complete the vector operation, free-of any other instructions issued from the instruction cache.

US Patent:

20050182915, Aug 18, 2005

Filed:

Feb 12, 2004

Appl. No.:

10/777934

Inventors:

Patrick Devaney - Haverhill MA, US
David Keaton - Boulder CO, US
Katsumi Murai - Osaka, JP

International Classification:

G06F015/00

US Classification:

712010000

Abstract:

A chip multiprocessor (CMP) includes a plurality of processors disposed on a peripheral region of a chip. Each processor has (a) a dual datapath for executing instructions, (b) a compiler controlled register file (RF), coupled to the dual datapath, for loading/storing operands of an instruction, and (c) a compiler controlled local memory (LM), a portion of the LM disposed to a left of the dual datapath and another portion of the LM disposed to a right of the dual datapath, for loading/storing operands of an instruction. The CMP also has a shared main memory disposed at a central region of the chip, a crossbar system for coupling the shared main memory to each of the processors, and a first-in-first-out (FIFO) system for transferring operands of an instruction among multiple processors.

US Patent:

20180371946, Dec 27, 2018

Filed:

Jun 26, 2017

Appl. No.:

15/633109

Inventors:

- Farmington CT, US
Patrick M. Devaney - Newington CT, US

International Classification:

F01D 25/24
F02C 3/04
F04D 29/52

Abstract:

A duct liner assembly for a gas turbine engine includes a first ring and a second ring. Also included is a first duct liner having a first end and a second end, the first duct liner mounted proximate the first end of the first duct liner to the first ring. Further included is a second duct liner having a first end and a second end, the second duct liner mounted proximate the second end of the second duct liner to the second ring. Yet further included is a coupling assembly including a threaded insert, a retaining bracket, and a threaded fastener extending through the retaining bracket and in threaded engagement with the threaded insert to couple the retaining bracket to the second duct liner.

US Patent:

20160298493, Oct 13, 2016

Filed:

Apr 13, 2015

Appl. No.:

14/685115

Inventors:

- Hartford CT, US
Michael D. Collier - Manchester CT, US
Patrick M. Devaney - Newington CT, US
Patrick M. Nadeau - Newington CT, US
Joseph J. Sedor - Oxford MA, US
Christopher Treat - Manchester CT, US

Assignee:

United Technologies Corporation - Hartford CT

International Classification:

F01D 25/26
F01D 25/28

Abstract:

A mid-turbine frame is provided. The mid-turbine frame may comprise an inner case having an annular surface with an interface section disposed on the annular surface. The interface section may include an interface feature. A balancing section may be disposed on the annular surface defining an opening and disposed circumferentially adjacent the interface section.