Patrick J Farrell

US Patent:

57450765, Apr 28, 1998

Filed:

Sep 5, 1996

Appl. No.:

8/708439

Inventors:

Thomas R. Turlington - Linthicum MD
Patrick G. Farrell - Baltimore MD
Gerald K. Kane - Stevensville MD
Gary L. Ferrell - Pasadena MD
Scott K. Suko - Elkridge MD
Joseph A. Faulkner - Ellicott City MD
Gregory K. Sinon - Dayton MD
Francis W. Hopwood - Severna Park MD
Andrew J. Piloto - Columbia MD

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H01Q 324

US Classification:

342372

Abstract:

A T/R module including a multilevel, multichip microwave package having a plurality of gallium arsenide monolithic microwave integrated circuit chips (MMICs) implementing RF switching elements, a variable phase shifter, a plurality of RF amplifiers, and gain trim attenuators and which are located on a planar RF assembly. The module's architecture includes shared or common MMIC circuit elements during both transmit and receive operation modes thus reducing the number of MMICs required while at the same time preloading the supply voltage regulator-modulator which supplies DC power to all the MMIC circuits without degrading T/R module efficiency.

US Patent:

60022795, Dec 14, 1999

Filed:

Oct 24, 1997

Appl. No.:

8/957694

Inventors:

William P. Evans - Catonsville MD
Eric Naviasky - Ellicott City MD
Patrick Farrell - Baltimore MD
Anthony Caviglia - Marriotsville MD
John Ebner - Baltimore MD
Hugh Thompson - Baltimore MD
Hao Tang - Silver Spring MD

Assignee:

G2 Networks, Inc. - Los Gatos CA

International Classification:

H03L 700

US Classification:

327144

Abstract:

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

US Patent:

55394132, Jul 23, 1996

Filed:

Sep 6, 1994

Appl. No.:

8/301201

Inventors:

Patrick Farrell - Baltimore MD
Jesus Chang - Elkridge MD
John Monk - Columbia MD
David Williams - Ellicott City MD
Joe Rocco - Columbia MD
Robert R. Angell - Greenbelt MD

Assignee:

Northrop Grumman - Los Angeles CA

International Classification:

H01Q 322

US Classification:

342372

Abstract:

An integrated circuit for use in a phased array antenna system having a central processing unit. The integrated circuit is associated with one of a plurality of antenna elements of the phased array antenna system. The integrated circuit includes an ID memory for storing a unique ID addressable by the central processing unit, and receives global commands from the central processing unit globally transmitted over a distributed serial bus. Upon detecting a global command, the integrated circuit compares an ID address associated with the global commands with the ID stored in the ID memory. The integrated circuit recognizes global commands as local commands to be executed locally when the ID address associated with the global commands is the same as the ID stored in the ID memory. In response to the local commands, the integrated circuit generates and provides control signals to the associated one of the antenna elements of the phased array antenna system.

US Patent:

59400315, Aug 17, 1999

Filed:

Apr 7, 1998

Appl. No.:

9/056094

Inventors:

Thomas R. Turlington - Linthicum MD
Patrick G. Farrell - Baltimore MD
Gerald K. Kane - Stevensville MD
Gary L. Ferrell - Pasadena MD
Scott K. Suko - Elkridge MD
Joseph A. Faulkner - Ellicott City MD
Gregory K. Sinon - Dayton MD
Francis W. Hopwood - Severna Park MD
Andrew J. Piloto - Columbia MD

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H01Q 324

US Classification:

342372

Abstract:

A T/R module including a multilevel, multichip microwave package having a plurality of gallium arsenide monolithic microwave integrated circuit chips (MMICs) implementing RF switching elements, a variable phase shifter, a plurality of RF amplifiers, and gain trim attenuators and which are located on a planar RF assembly. The module's architecture includes shared or common MMIC circuit elements during both transmit and receive operation modes thus reducing the number of MMICs required while at the same time preloading the supply voltage regulator-modulator which supplies DC power to all the MMIC circuits without degrading T/R module efficiency.