Patrick Kelley

US Patent:

8177644, May 15, 2012

Filed:

Aug 15, 2007

Appl. No.:

12/377531

Inventors:

Peter R. Anderson - Glenview IL, US
Rory L. Block - Carson City NV, US
Joel R. Jaffe - Glenview IL, US
Shridhar P. Joshi - Naperville IL, US
Vincent Chan - Vancouver, CA
Patrick H. Kelley - Evanston IL, US
Richard T. Schwartz - Chicago IL, US
Byron A. Uytiepo - Chicago IL, US

Assignee:

WMS Gaming Inc. - Waukegan IL

International Classification:

A63F 9/24

US Classification:

463 40

Abstract:

A gaming system and method of conducting a wagering game having a fantasy-sports feature on a gaming system is disclosed. A wager is received from a user to play the wagering game. A roster having one or more player is created, via user selection. A projected team score and an actual team score for the created roster are determined. A ratio is calculated for the actual team score to the projected team score. An award is provided to the user if the calculated ratio meets a predetermined criterion.

US Patent:

62845985, Sep 4, 2001

Filed:

Nov 23, 1999

Appl. No.:

9/447893

Inventors:

Patrick J. Kelley - Orlando FL
Ranbir Singh - Orlando FL
Larry B. Fritzinger - Orlando FL
Cynthia C. Lee - Orlando FL
John Simon Molloy - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 31336

US Classification:

438257

Abstract:

A method of forming round corners for a gate oxide between a floating gate and a control gate of a memory cell comprises the steps of forming the floating gate over a tunnel oxide; forming a mask over the floating gate; forming rounded end caps adjacent distal ends of the mask; transferring the rounding of the end caps to top corners of the floating gate; forming the gate oxide over the floating gate; and, forming the control gate over the gate oxide. A memory cell having a rounded corner interface between the floating gate and control gate is also provided.

US Patent:

62227645, Apr 24, 2001

Filed:

Dec 13, 1999

Appl. No.:

9/460160

Inventors:

Patrick J. Kelley - Orlando FL
Chung Wai Leung - Orlando FL
Ranbir Singh - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Murray Hill NJ

International Classification:

G11C 1604

US Classification:

36518507

Abstract:

An electrically erasable memory device includes a substrate and a plurality of single poly layer memory cells in the substrate. Each single poly layer memory cell includes a first MOS transistor in a first region in the substrate and spaced apart source and drain regions. Each single poly layer memory cell further includes a capacitor having a first electrode overlying a second region in the substrate and an insulating layer therebetween, and a third region in the second region defining a second electrode. An erasing circuit selectively erases the single poly layer memory cell by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode of the capacitor. The first and second voltage references bias the first MOS transistor so that the third voltage reference for erasing the single poly layer memory cell does not cause a junction breakdown of the first MOS transistor.

US Patent:

63135000, Nov 6, 2001

Filed:

Dec 14, 1999

Appl. No.:

9/460812

Inventors:

Patrick J. Kelley - Orlando FL
Chung Wai Leung - Orlando FL
Ranbir Singh - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 29788

US Classification:

257316

Abstract:

A split gate memory cell is described which is fabricated from two-polysilicon layers and comprises a silicon substrate having a source and a drain electrode and a storage node, a tunnel oxide on the substrate, a first control gate electrode and a floating gate electrode spaced from each other and fabricated from the same polysilicon layer and a second control gate electrode of a second poly material formed between and over the first control gate and floating gate and isolated therefrom by a dielectric layer therebetween.

US Patent:

61919802, Feb 20, 2001

Filed:

May 31, 2000

Appl. No.:

9/583505

Inventors:

Patrick J. Kelley - Orlando FL
Ross A. Kohler - Allentown PA
Chung W. Leung - Orlando FL
Richard J. McPartland - Nazareth PA
Ranbir Singh - Orlando FL

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

G11C 1604

US Classification:

36518529

Abstract:

A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e. g. , 15 volts) is greater than a typical erase voltage (e. g. , 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e. g. , 0. 25-micron and lower).

US Patent:

61747866, Jan 16, 2001

Filed:

Nov 23, 1999

Appl. No.:

9/447154

Inventors:

Patrick J. Kelley - Orlando FL
Ranbir Singh - Orlando FL
Larry B. Fritzinger - Orlando FL
Cynthia C. Lee - Orlando FL
John Simon Molloy - Orlando FL

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

H01L 2176

US Classification:

438425

Abstract:

A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench.

US Patent:

61689955, Jan 2, 2001

Filed:

Dec 14, 1999

Appl. No.:

9/460652

Inventors:

Patrick J. Kelley - Orlando FL
Chung Wai Leung - Orlando FL
Ranbir Singh - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 218247

US Classification:

438266

Abstract:

A method of fabricating a novel split gate memory cell comprises forming a tunnel oxide layer on a silicon substrate, forming a first conductive layer over said tunnel oxide layer, etching a trench in said conductive layer to divide said conductive layer into two separate layers with a space therebetween, one such layer to become a first gate electrode and the other separate layer to become a floating gate electrode of the device, forming a dielectric layer over the exposed surfaces, and depositing a second conductive layer which will become a second control gate electrode over said dielectric layer.