Patrick J O'Brien

US Patent:

20120096777, Apr 26, 2012

Filed:

May 13, 2011

Appl. No.:

13/107118

Inventors:

Karl BACKUS - Emeryville CA, US
George Bradley - San Francisco CA, US
Tim Eliassen - Sunapee NH, US
Timothy W. Gudgel - Palo Alto CA, US
Scott David Hazard - Campbell CA, US
Holger Krueger - Schwabmuenchen, DE
Marcin Marchewka - London, GB
Michael Mulhern - Westford MA, US
Patrick O'Brien - West Nyack NY, US
James O'Callaghan - Winchester, GB
Yutang Zhang - Beijing City, CN

Assignee:

Apple Inc. - Cupertino CA

International Classification:

E04B 7/10
E04B 1/32
E04C 3/02
E04C 3/38
E04H 14/00

US Classification:

52 801, 52633, 521731, 52639, 52831

Abstract:

The present invention relates to support structures including truss assemblies and purlins, the truss assemblies including struts, wherein utilities such as pipes and cables can be contained within the purlins, and can pass through openings in the struts, to thereby be retained by the support structures so as to be hidden from view.

US Patent:

20120143641, Jun 7, 2012

Filed:

Dec 5, 2011

Appl. No.:

13/311385

Inventors:

Patrick J. O'Brien - San Ramon CA, US

International Classification:

G06Q 10/00

US Classification:

705 711

Abstract:

The present invention relates to systems and methods for computing business value, thereby enable interested parties to accurately and efficiently determine the value of a given solution to a stakeholder. The system collates solution attributes. The solution may include any goods or services that a vendor, or other supplier, is offering to a purchaser. The solution attributes include the cost of the solution, the areas of a business that the solution impacts and degree of improvement that the solution provides to key performance indicators that are relevant to the areas impacted. The system also provides community aggregated values for the key performance indicators and other metrics for the impacted areas. The system collates stakeholder specific information, including revenue for the stakeholder and key objectives.

US Patent:

54666350, Nov 14, 1995

Filed:

Jun 2, 1994

Appl. No.:

8/252691

Inventors:

Brian Lynch - Milpitas CA
Patrick O'Brien - Palo Alto CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21283
H01L 21441

US Classification:

437183

Abstract:

An interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

US Patent:

57548404, May 19, 1998

Filed:

Jan 23, 1996

Appl. No.:

8/590082

Inventors:

Kevin G. Rivette - Palo Alto CA
Irving S. Rappaport - Palo Alto CA
Patrick O'Brien - Half Moon Bay CA

Assignee:

SmartPatents, Inc. - Menlo Park CA

International Classification:

G06F 1730

US Classification:

395602

Abstract:

A system and method for assisting in the preparation of a document, and for analyzing a document, such as a patent or patent application, are described herein. The system aids a user to verify that terms in a patent application are being used consistently. The system also facilitates editing of the patent application so as to achieve terminology consistency. The system operates by allowing a user to select a document containing a patent application. The user then selects the specification portion of the patent application, and also selects the claims portion of the patent application. The system indexes the specification portion and the claims portion to thereby generate a merged index table. The system analyzes the merged index table to identify terms in the claims portion that are not present in the specification portion, and then displays these terms (called claim terms). A user can then edit the patent application so as to properly describe these terms in the specification.

US Patent:

58724044, Feb 16, 1999

Filed:

Feb 6, 1997

Appl. No.:

8/795107

Inventors:

Brian Lynch - Milpitas CA
Patrick O'Brien - Palo Alto CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348
H01L 2352
H01L 2940

US Classification:

257781

Abstract:

An interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

US Patent:

54472296, Sep 5, 1995

Filed:

Jun 28, 1993

Appl. No.:

8/085260

Inventors:

Brian Lynch - Milpitas CA
Patrick O'Brien - Palo Alto CA
Adrian Murphy - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

B65D 8542

US Classification:

206706

Abstract:

Industry-standard COT/TAB integrated circuit part carrier frame members are receivable into a shipping tube member in a stack which rests at one end on paired retaining pins and at the other end is retained by a closure member of the shipping tube. As so disposed in the shipping tube, the carrier frames are securely held with virtually no risk that they will slip out of place within the shipping tube. The shipping tube member includes side walls which define plural pairs of apertures spaced along the length of the shipping tube so that: the paired pins may be relocated to adapt the shipping tube to various shipment sizes. The remainder of the shipping tube remains empty to reduce both the cost of carrier frames conventionally used just as filler, as well as reducing shipping costs by eliminating the weight of these filler carrier frames which are shipped empty.

US Patent:

6014663, Jan 11, 2000

Filed:

Apr 10, 1998

Appl. No.:

9/058347

Inventors:

Kevin G. Rivette - Palo Alto CA
Irving S. Rappaport - Palo Alto CA
Patrick O'Brien - Half Moon Bay CA

Assignee:

Aurigin Systems, Inc. - Mountain View CA

International Classification:

G06F 1730

US Classification:

707 4

Abstract:

A system and method for assisting in the preparation of a document, and for analyzing a document, such as a patent or patent application, are described herein. The system aids a user to verify that terms in a patent application are being used consistently. The system also facilitates editing of the patent application so as to achieve terminology consistency. The system operates by allowing a user to select a document containing a patent application. The user then selects the specification portion of the patent application, and also selects the claims portion of the patent application. The system indexes the specification portion and the claims portion to thereby generate a merged index table. The system analyzes the merged index table to identify terms in the claims portion that are not present in the specification portion, and then displays these terms (called claim terms). A user can then edit the patent application so as to properly describe these terms in the specification.

US Patent:

56984650, Dec 16, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/474305

Inventors:

Brian Lynch - Milpitas CA
Patrick O'Brien - Palo Alto CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21283
H01L 2158
H01L 2160

US Classification:

437183

Abstract:

A process where in an interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.