Patrick E Perry

US Patent:

6477654, Nov 5, 2002

Filed:

Apr 6, 1999

Appl. No.:

09/287159

Inventors:

Alvar Antonio Dean - Essex Junction VT
Patrick Edward Perry - Shelburne VT
Sebastian Theodore Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 132

US Classification:

713300, 713322

Abstract:

An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of the integrated circuit. Special power control instructions are added to user applications in order to control via the power control unit, the power consumption of the different functional units.

US Patent:

6479974, Nov 12, 2002

Filed:

Dec 28, 2000

Appl. No.:

09/750884

Inventors:

John Maxwell Cohn - Richmond VT
Alvar Antonio Dean - Essex Junction VT
David James Hathaway - Underhill Center VT
Patrick Edward Perry - Shelburne VT
Sebastian Theodore Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05F 304

US Classification:

323312, 327530

Abstract:

A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

US Patent:

6678847, Jan 13, 2004

Filed:

Apr 30, 1999

Appl. No.:

09/303211

Inventors:

Patrick E. Perry - Shelburne VT
Sebastian T. Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714727, 714729, 714731

Abstract:

A system and method for determining the operational state of a logic device having a plurality of shadow registers, each associated with one of a plurality of functional registers. Data stored in a functional register is, under selected conditions, also stored in an associated shadow register. These conditions include without limitation receipt by the functional register of predetermined event information such as an opcode, memory address or other information. Data in a given set of functional registers, e. g. , registers making up pipeline stages in a microprocessor, may be stored in shadow registers simultaneously or sequentially when given data reaches a given register in the set. Additionally, data is stored in the shadow registers without interrupting execution cycles of the logic device.

US Patent:

6711719, Mar 23, 2004

Filed:

Aug 13, 2001

Appl. No.:

09/928573

Inventors:

John Maxwell Cohn - Richmond VT
Alvar A. Dean - Groton MA
Amir H. Farrahi - Peekskill NY
David J. Hathaway - Underhill Center VT
Thomas Michael Lepsic - Jeffersonville VT
Patrick Edward Perry - Shelburne VT
Scott A. Tetreault - Clinton MA
Sebastian T. Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 2, 716 4, 716 7, 716 10

Abstract:

In integrated circuit (IC) designs, a component of power consumed may be represented as Power=Â FCV , where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

US Patent:

6802033, Oct 5, 2004

Filed:

Apr 6, 1999

Appl. No.:

09/286855

Inventors:

Claude L. Bertin - South Burlington VT
Alvar A. Dean - Essex Junction VT
Kenneth J. Goodnow - Essex Junction VT
Scott W. Gould - South Burlington VT
Patrick E. Perry - Essex Junction VT
Wilbur D. Pricer - Charlotte VT
William R. Tonti - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714704, 370311

Abstract:

A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

US Patent:

6880074, Apr 12, 2005

Filed:

Dec 22, 2000

Appl. No.:

09/681077

Inventors:

Patrick E. Perry - Shelburne VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/45
G06F009/54
G06F009/445

US Classification:

712248, 712213, 712229, 712227, 717131, 717161

Abstract:

Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.

US Patent:

20070271034, Nov 22, 2007

Filed:

May 17, 2006

Appl. No.:

11/383786

Inventors:

Patrick E. Perry - Shelburne VT, US

International Classification:

G01C 21/34

US Classification:

701209, 701202, 34099519

Abstract:

Disclosed herein is a method of route planning for global positioning system (GPS) based navigation systems. The method identifies route segments used in a GPS based navigation system and records an actual historical time of travel for at least one route segment traveled by users of the GPS based navigation system travel. The actual historical time of travel comprises the amount of time taken by a user of the GPS based navigation system to go from a beginning of the route segment to an end of the route segment. With embodiments herein, the day and time that the route segment was recorded is also noted. Then, the actual historical time of travel and the day and time for the route segment can be stored in a database. This information can be stored for a single-user or can be combined from a plurality users of the GPS based navigation systems.

US Patent:

20080215237, Sep 4, 2008

Filed:

Mar 25, 2008

Appl. No.:

12/054685

Inventors:

Patrick E. Perry - Shelburne VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G01C 21/34
G01S 5/00

US Classification:

701209

Abstract:

Disclosed herein is a design structure for route planning for global positioning system (GPS) based navigation systems. The method identifies route segments used in a GPS based navigation system and records an actual historical time of travel for at least one route segment traveled by users of the GPS based navigation system travel. The actual historical time of travel comprises the amount of time taken by a user of the GPS based navigation system to go from a beginning of the route segment to an end of the route segment. With embodiments herein, the day and time that the route segment was recorded is also noted. Then, the actual historical time of travel and the day and time for the route segment can be stored in a database. This information can be stored for a single-user or can be combined from a plurality users of the GPS based navigation systems.