Patrick J Quirk

US Patent:

6892339, May 10, 2005

Filed:

Sep 20, 1999

Appl. No.:

09/398707

Inventors:

Lee T. Gusler - Madison AL, US
Patrick J. Quirk - Huntsville AL, US
Ronald M. Zuckerman - Madison AL, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F011/00
G06F011/30
G08C025/00
H03M013/00
H04L001/00

US Classification:

714746, 714758

Abstract:

The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP ) and a general purpose host central processing unit (CPU ). The DSP () handles all front end data pump processing such as interface to an analog front end (and ), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU () handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP () and the CPU () to communicate with each other effectively, buffers () under the control of specialized buffer management methodology (FIG. ) are used.

US Patent:

7254766, Aug 7, 2007

Filed:

Mar 30, 2005

Appl. No.:

11/093520

Inventors:

Lee T. Gusler - Madison AL, US
Patrick J. Quirk - Huntsville AL, US
Ronald M. Zuckerman - Madison AL, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G08C 25/02
H04L 1/18

US Classification:

714748, 714776

Abstract:

The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP ) and a general purpose host central processing unit (CPU ). The DSP () handles all front end data pump processing such as interface to an analog front end ( and ), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU () handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP () and the CPU () to communicate with each other effectively, buffers () under the control of specialized buffer management methodology (FIG. ) are used.

US Patent:

7471531, Dec 30, 2008

Filed:

Aug 22, 2006

Appl. No.:

11/507798

Inventors:

Matthew Blaha - Holmdel NJ, US
Albert Molina - Alcobendad, ES
Patrick J. Quirk - Huntsville AL, US
Fadi Saibi - Hoboken NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H02M 7/537

US Classification:

363 97, 363 2113, 363 2116

Abstract:

Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

US Patent:

7643315, Jan 5, 2010

Filed:

Nov 19, 2008

Appl. No.:

12/313344

Inventors:

Matthew Blaha - Holmdel NJ, US
Albert Molina - Alcobendad, ES
Patrick J. Quirk - Huntsville AL, US
Fadi Saibi - Hoboken NJ, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H02M 3/335

US Classification:

363 2113, 363 2116, 363 97

Abstract:

Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

US Patent:

7685440, Mar 23, 2010

Filed:

Mar 6, 2006

Appl. No.:

11/369057

Inventors:

Matthew Blaha - Holmdel NJ, US
Patrick J. Quirk - Huntsville AL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 1/26

US Classification:

713300, 710303

Abstract:

In one embodiment, the invention is an apparatus (e. g. , an Ethernet switch) having an isolated side and a line side. A line-side connector is connectable to a cable. An isolated-side physical-layer module (1) is electrically coupled to the connector via a signal-isolation transformer and (2) processes signals transmitted over the cable. A line-side power conditioning module (1) is electrically coupled to an isolated-side power switcher via a power-isolation transformer that converts an AC power signal received from the power switcher into a transformed AC power signal and (2) converts the transformed AC power signal into a cable power signal to be supplied via the connector to the cable in order to power a cable-powered device connected to the cable. An isolated-side control module performs a detection function in which the control module determines whether or not a cable-powered device is connected to the cable.

US Patent:

7774584, Aug 10, 2010

Filed:

Jun 27, 2007

Appl. No.:

11/769376

Inventors:

Lee T. Gusler - Madison AL, US
Patrick J. Quirk - Huntsville AL, US
Ronald M. Zuckerman - Madison AL, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/30

US Classification:

712220, 714776, 708550

Abstract:

The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP ) and a general purpose host central processing unit (CPU ). The DSP () handles all front end data pump processing such as interface to an analog front end ( and ), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU () handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP () and the CPU () to communicate with each other effectively, buffers () under the control of specialized buffer management methodology (FIG. ) are used.

US Patent:

7843670, Nov 30, 2010

Filed:

Sep 29, 2006

Appl. No.:

11/536770

Inventors:

Matthew Blaha - Holmdel NJ, US
Luis de la Torre - Daganzo de Arriba, ES
Patrick J. Quirk - Huntsville AL, US
Fadi Saibi - Hoboken NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H02H 7/00

US Classification:

361 18, 361 931

Abstract:

One embodiment monitors a line-side electrical current provided by a power sourcing equipment (PSE) port to a powered device (PD), the PSE port having a power-isolation transformer with a primary coil on an isolated side and a secondary coil on a line side. A switching signal having a switching period and a duty cycle is applied to the primary coil of the power-isolation transformer. A value is determined for an electrical current on the isolated side of the power-isolation transformer, conversion is performed between a line-side electrical current value Iand a corresponding isolated-side peak-current value I, and the line-side electrical current is indirectly monitored based on the determined isolated-side current value.

US Patent:

8132027, Mar 6, 2012

Filed:

Jun 16, 2006

Appl. No.:

11/917261

Inventors:

Matthew Blaha - Holmdel NJ, US
Luis de La Torre - Daganzo de Arriba, ES
Alan L. Ellis - San Jose CA, US
Patrick J. Quirk - Huntsville AL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 1/00

US Classification:

713300

Abstract:

In one embodiment, a powered device (PD) () has a PHY module () and a media access controller () (MAC), the PD () adapted to connect to power sourcing equipment (PSE) via a cable, () where the PD () is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD () extracts () from the cable () a DC signal used to power the PD without using a transformer. Capacitors () located in the signal paths between the MAC () and the cable () support electrical isolation of the MAC ().